SNOSDB6D December   2020  – October 2024 LMP7704-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 5 V
    6. 5.6 Electrical Characteristics VS = 10 V
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Radiation Hardened Performance
      2. 6.3.2 Engineering Model (Devices With /EM Suffix)
      3. 6.3.3 Diodes Between the Inputs
      4. 6.3.4 Capacitive Load
      5. 6.3.5 Input Capacitance
    4. 6.4 Device Functional Modes
      1. 6.4.1 Precision Current Source
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Low Input Voltage Noise
      2. 7.1.2 Total Noise Contribution
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics VS = 10 V

at TA = +25°C, VS = (V+) – (V–) = 10 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±60 ±260 µV
TA = –55°C to +125°C ±520
dVOS/dT Input offset voltage drift(1) TA = –55°C to +125°C ±1 ±5 µV/°C
PSRR Power-supply rejection ratio 2.7 V < VS < 12 V 86 100 dB
TA = –55°C to +125°C 82 dB
Flight model post-HDR exposure 82 dB
INPUT BIAS CURRENT
IB Input bias current ±1 ±10 pA
TA = –55°C to +125°C ±400
Flight model post-TID exposure ±400
IOS Input offset current ±40 fA
NOISE
en Input voltage noise density f = 1 kHz 9 nV/√Hz
in Input current noise density f = 100 kHz 1 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage(2) TA = –55°C to +125°C (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio (V–) < VCM < (V+)  90 130 dB
TA = –55°C to +125°C 86
Flight model post-HDR exposure,
TA = –55°C to +125°C		 83
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.3 V < VOUT < (V+) – 0.3 V,
RL = 2 kΩ		 100 121 dB
TA = –55°C to +125°C 94

(V–) + 0.2 V < VOUT < (V+) – 0.2 V		 100 134
TA = –55°C to +125°C 97
FREQUENCY RESPONSE
GBW Gain bandwidth 2.5 MHz
SR Slew rate G = 1, 9-V step, 10% to 90% rising 0.8 V/µs
THD+N Total harmonic distortion + noise G = 1, f = 1 kHz 0.02%
OUTPUT
VO Voltage output swing from rail Positive rail, RL = 2 kΩ to VS / 2 60 120 mV
TA = –55°C to +125°C 200
Positive rail 40 60
TA = –55°C to +125°C 120
Negative rail, RL = 2 kΩ to VS / 2 50 120
TA = –55°C to +125°C 190
Negative rail 30 50
TA = –55°C to +125°C 100
ISC Short-circuit current VOUT = VS / 2, VIN = ±100 mV +86 / –84 mA
POWER SUPPLY
IQ Total quiescent current IO = 0 A 3.2 4.2 mA
TA = –55°C to +125°C 5.7
(1) Specification set by device characterization, not tested in final production.
(2) Common-mode voltage per channel is described by 0.5 × (VIN A+ + VIN A–), 0.5 × (VIN B+ + VIN B–), 0.5 × (VIN C+ + VIN C–), or 0.5 × (VIN D+ + VIN D–). Respect per-channel differential voltage limitations. See also Section 6.3.3.