SNOSDJ1A
July 2024 – October 2024
LMG2100R026
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Parameter Measurement Information
6.1
Propagation Delay and Mismatch Measurement
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Control Inputs
7.3.2
Start-Up and UVLO
7.3.3
Bootstrap Supply Voltage Clamping
7.3.4
Level Shift
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
VCC Bypass Capacitor
8.2.2.2
Bootstrap Capacitor
8.2.2.3
Slew Rate Control
8.2.2.4
Power Dissipation
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Examples
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Package Information
1
Features
Integrated half-bridge GaN FETs and driver
93V continuous, 100V pulsed voltage rating
Package optimized for easy PCB layout
High slew rate switching with low ringing
5V external bias power supply
Supports 3.3V and 5V input logic levels
Gate driver capable of up to 10MHz switching
Excellent propagation delay (33ns typical) and matching (2ns typical)
Internal bootstrap supply voltage clamping to prevent GaN FET overdrive
Supply rail undervoltage for lockout protection
Low power consumption
Exposed top QFN package for top-side cooling
Large GND pad for bottom-side cooling