SNOU180A June   2021  – September 2021 LM74701-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 I/O Connector Description
    2. 2.2 Board Setup
    3. 2.3 Schematic
  4. 3LM74701-Q1EVM Performance Capture
    1. 3.1 LM74701-Q1EVM Startup
    2. 3.2 Startup Reverse Polarity (–12 V)
    3. 3.3 ISO 7637-2 Pulse 1 Performance
  5. 4EVM Board Assembly Drawings and Layout Guidelines
    1. 4.1 PCB Drawings
    2. 4.2 Bill of Materials
  6. 5Revision History

3.1 LM74701-Q1EVM Startup

  • A startup pulse from 0 V to 12 V is applied at the input of the LM74701-Q1EVM.
  • Figure 3-1 shows the input voltage (CH2) rises from 0 V to 12 V and the gate voltage (CH3) comes up after input voltage crosses device PoR threshold .
  • The gate of external N-FET is fully enhanced and FET is turned on. Output voltage (CH1) rises smoothly from 0 V to 12 V.
GUID-20210601-CA0I-DL1Z-FZFQ-CNSLLVSTJHPX-low.png Figure 3-1 LM74701-Q1EVM Startup