SNOU201 February   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Recommended Equipment Setup
    2. 2.2 Board Setup
      1. 2.2.1 Power Supplies
      2. 2.2.2 Inputs and Outputs
  7. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks

1.3 Specification

GUID-20240220-SS0I-FBZS-9QRQ-JTWFVBTGBHQQ-low.svg Figure 1-1 TLV1872EVM Block Diagram
  • Input supply range (VCCI-VEEI): +2.7 V to +36 V
  • Output negative supply voltage (VEEO): VEEI to (VEEI + 18V)
  • Output positive supply voltage (VCCO): VEEO + (2.7V to VCCI)
  • Input common mode voltage range: (VEEI - 0.2V) to (VCCI + 0.2V)
Table 1-1 TLV1872EVM Test Point to DUT Pin Mapping
TLV3607EVM CONNECTIONS

Test point 1 and 4

Pin header 1

 VEEO (Pin 1)

Test point 7

Pin header 2

 OUT1 (Pin 2)
Pin header 3 IN1- (Pin 3)

Test point 5

Pin header 4

 IN1+ (Pin 4)

Test point 3

Pin header 5

 VEEI (Pin 5)

Test point 6

Pin header 6

 IN2+ (Pin 6)
Pin header 7 IN2- (Pin 7)

Test point 8

Pin header 8

 OUT2 (Pin 8)

Test point 9

Pin header 9

 VCCI (Pin 9)

Test point 2

Pin header 10

 VCCO (Pin 10)