SNOU205 December   2024 LMG2650

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 General TI High Voltage Evaluation User Safety Guidelines
      1. 1.5.1 Safety and Precautions
  7. 2Hardware
    1. 2.1 LMG2650EVM-100 Daughtercard
      1. 2.1.1 Test Points
      2. 2.1.2 Integrated Current Sensing
      3. 2.1.3 Enable Pin
      4. 2.1.4 GDH
      5. 2.1.5 Power Pins
      6. 2.1.6 Heat Sink
    2. 2.2 Motherboard
      1. 2.2.1 Bias Supply
      2. 2.2.2 PWM Input
      3. 2.2.3 Fault Protection
    3. 2.3 Recommended Footprint
    4. 2.4 Test Equipment
    5. 2.5 Test Procedure When Paired With LMG342X-BB-EVM
      1. 2.5.1 Setup
      2. 2.5.2 Start-Up and Operating Procedure
      3. 2.5.3 Test Results
      4. 2.5.4 Shutdown Procedure
      5. 2.5.5 Additional Operating Notes
  8. 3Hardware Design Files
    1. 3.1 LMG2650EVM-100 Schematic
    2. 3.2 Motherboard Schematic
    3. 3.3 PCB Layout
    4. 3.4 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Related Documentation

2.1 LMG2650EVM-100 Daughtercard

The LMG2650EVM-100 has one LMG2650 device with two GaN FETs in a half-bridge configuration. All the bias and level shifting components are included, which allows low-side referenced signals to control both FETs. High-frequency decoupling capacitors are included on the power stage in an optimized layout to minimize parasitic inductance and reduce voltage overshoot.

The layout of the board is critical to the performance and functionality of the device. TI recommends a four-layer or higher layer count board to reduce the parasitic inductance of the layout to the best performance. Layout guidelines are provided in the LMG2650 650V 95mΩ GaN Half Bridge with Integrated Driver and Current Sense Emulation data sheet to optimize the solder-joint reliability, power loop inductance, signal to ground connection, switched-node capacitance and thermal heat dissipation.

There is a 12 logic pin header on the LMG2650EVM-100 with 8 pins used for active logic and 4 with no connections

Table 2-1 Logic Pin Function Description
PINPIN DESIGNATIONDESCRIPTION
LS PWM1Logic gate signal input for low-side LMG2650. Compatible with both 3.3V and 5V logic. Referenced to AGND.
HS PWM8Logic gate signal input for high-side LMG2650. Compatible with both 3.3V and 5V logic. Referenced to AGND.
12V9Auxiliary power input for LMG2650EVM-100.
5V3,6,105V auxiliary power for FAULT signal pull-up resistor and circuit debugging.
AGND11,12Logic and bias power ground return pin. Functionally isolated from PGND.

There are six power pins on the LMG2650EVM-100.

Table 2-2 Power Pin Function Description
PINDESCRIPTION
SWSwitch node of the half-bridge configuration.
HVInput DC voltage of the half-bridge configuration.
PGNDPower ground of the half-bridge configuration. Functionally isolated from AGND.
CAUTION:

High-voltage levels are present on the evaluation module whenever energized. Take proper precautions when working with the EVM.

LMG2650EVM-100 LMG2650EVM Block Diagram Figure 2-1 LMG2650EVM Block Diagram