SNVA453B August 2011 – January 2022 LM10500
The LM10500 evaluation board can also interface to an AVS-compatible primary controller using J1. All signals related to the PWI signaling environment are available on this 1x9 header on the edge of the board. Although primarily intended for signal inspection, this header also allows external control of the PWI communication. This connector allows the LM10500 to be tested in a closed AVS loop with a primary controller, such as AVS compatible ASICs, SoCs, and processors.
The pin list of J1 is shown in the following table.
| Pin | Label | Type | Description |
|---|---|---|---|
| 1 | GND | GND | Ground |
| 2 | VBAT | Power | VBAT or sense |
| 3 | PWROK | Output | PWROK |
| 4 | RESETN | Input | 1: Active 0: Reset |
| 5 | ENABLE | Input | 1: Enabled 0: Disabled |
| 6 | SPWI | Input/Output | PWI data |
| 7 | SCLK | Input | PWI clock |
| 8 | VPWI | Power | VPWI-EXT or sense |
| 9 | GND | GND | Ground |
The pins are spaced at 100-mil intervals. They can also be used as a sensing pin to determine the drive level for the PWI interface pins: SCLK, SPWI, PWROK, ENABLE, and RESETN. VBAT and VPWI should be used as the control voltage input when the USB2PWI board is not connected. SPWI and SCLK are PWI communication data pin and clock pin, respectively. ENABLE is connected to the EN pin of the device. It is pulled up to AVIN through a 10-kΩ resistor on the board. This pin also can be used to enable/disable the device externally. If driven externally, a voltage typically greater than 1.2 V will enable the device. VPWI is for powering VPWI pin externally or monitoring the VPWI pin. VPWI range is from (1.8 V– 10%) to (3.3 V + 10%).