SNVA790A October   2020  – July 2022 LMR36520

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2 Fly-Buck Converter Device Operation
    1. 2.1 Output Current Equations and Considerations
  5. 3LMR36520 Fly-Buck Converter Design
    1. 3.1 Coupled Inductor
    2. 3.2 Primary Output Capacitor
    3. 3.3 Rectifying Diode
    4. 3.4 Secondary Output Capacitor
    5. 3.5 Preload Resistor
    6. 3.6 Zener Diode
    7. 3.7 Snubber Circuit
  6. 4Experimental Results
    1. 4.1 Steady State
    2. 4.2 Secondary Output Voltage
    3. 4.3 Load Transient
    4. 4.4 Start-up
    5. 4.5 Output Current
  7. 5Conclusion
  8. 6References
  9. 7Revision History

3.2 Primary Output Capacitor

The primary output capacitor determines the amount of output voltage ripple and load transient performance that the regulator can achieve on its primary output. Equation 21, Equation 22, Equation 23 and can be used to estimate the lower bound of the output capacitance and upper bound of the capacitor ESR.

Equation 21. C o u t ≥ ∆ I o u t f s w × ∆ V o u t × K × 1 - D × 1 + K + K 2 12 × ( 2 - D )
Equation 36. E S R ≤ 2 + K × ∆ V o u t 2 × ∆ I o u t 1 + K + K 2 12 × 1 + 1 ( 1 - D )
Equation 23. D = V o u t V i n

where

  • ΔVout = output voltage transient
  • ΔIout = output current transient
  • K = ripple factor

Although not specified in Table 3-1, let ΔIout = 0.5 A and ΔVout = 20 mV, while K ≅ 0.5 from the previous section. Solving for Cout and ESR:

Equation 24. C o u t ≥ 97.6   μ F
Equation 25. E S R ≤ 32   m Ω

Selecting two 47-μF multilayer ceramic capacitors to be placed in parallel will result in slightly lower output capacitance than Equation 24 and, therefore, higher output voltage ripple, but this is acceptable for this design.

Using Equation 26 to approximate the output voltage ripple results in:

Equation 26. V r ≅ ∆ I L × E S R 2 + 1 8 × f s w × C O U T 2
Equation 27. V r ≅ 0.015   V p k - p k

This expected voltage ripple in Equation 27 is less than 1% of the desired output voltage so this is acceptable for most applications.

To reduce high frequency noise on the primary output, an additional high frequency capacitor of around 100 nF can also be placed at the output.

All of the primary output capacitors should have a voltage rating greater than that of the desired output voltage and may have to be rated higher in order to account for de-rating associated with DC bias and temperature. Consult the capacitor data sheet to ensure output capacitance does not significantly de-rate at the desired output voltage and temperature conditions. A voltage rating of 16 V to 25 V is appropriate for this application.

The RMS current rating of the primary output capacitor is another important parameter that must be met in order to ensure proper operation. The figure below shows the straight line approximations of the AC current waveforms through the primary and secondary output capacitors. The RMS values of these current waveforms can be estimated using the piecewise linear approximation method which is detailed below.

Figure 3-2 Straight Line Approximation of AC Current Through Output Capacitors
Equation 28. i p r i _ c o u t _ r m s = y 2 + x 2 + x * y 3 × t o n T × x 2 + z 2 + x * z 3 × t o f f T
Equation 29. x = I p r i _ p o s p k = 1.244   A
Equation 30. y = I o u t 1 - ∆ i m 2 = 0.256   A
Equation 31. z = I p r i _ n e g p k - I o u t 1 = - 1.244   A
Equation 32. i p r i _ c o u t _ r m s = 0.761   A r m s

Equation 32 represents the AC current that will be split amongst the primary output capacitors. Therefore, the two 47-μF ceramic capacitors selected for the primary output capacitor bank are expected to have about 380 mArms current through them and should be rated higher than this.