SNVAA47 May   2022 LP8732-Q1 , LP87521-Q1 , LP87524-Q1 , LP87561-Q1 , LP87562-Q1

 

  1. 1Abstract
    1.     Trademarks
  2. 1Design Parameters
  3. 2Power Solution
  4. 3Sequencing
    1. 3.1 Startup, Application Processor
    2. 3.2 Shutdown, Application Processor
    3. 3.3 Startup, Safety
    4. 3.4 Shutdown, Safety
    5. 3.5 Startup, RTC
    6. 3.6 Shutdown, RTC
  5. 4Schematic
  6. 5Software Drivers
  7. 6Recommended External Components
  8. 7Measurements
  9. 8Summary
  10. 9References

2 Power Solution

Figure 2-1 shows power tree with LP875610B-Q1, LP87562R-Q1, LP87521S-Q1, LP875241J-Q1, and TPS74501-Q1 devices powering the X9P/U application processor rails.

Figure 2-2 shows power tree with LP873248-Q1 PMIC powering the X9P/U safety rails.

Figure 2-3 shows power tree with two TPS74501-Q1 LDOs powering the X9P/U RTC rails.

Figure 2-1 Semidrive X9P/U AP Power Block Diagram

Main features:

  • 5 V supplied from pre-regulator
  • After the devices are powered, the microcontroller or preregulator PGOOD can set the SYS_CTRL0 high to initiate the startup sequence for application processor rails.
  • Startup and or shutdown delays are controlled internally in the LP875x-Q1 sequencers and discrete LDO is controlled with PMIC GPIO with pre-set delays.
  • I2C can be used to read status registers and reset interrupts.
  • PMIC devices have dedicated I2C address so they can share the same I2C bus.
  • Combined PG signal from LP875x-Q1 and TPS74501-Q1 act as AP_RESET_EN signal for the SoC. Any failure on the rail voltages will keep the SoC in reset state until fault is cleared.
Figure 2-2 Semidrive X9P/U Safety Power Block Diagram

Main features:

  • 5 V supplied from pre-regulator
  • After the devices are powered, the microcontroller or preregulator PGOOD can set the SYS_PWR_ON high to initiate the startup sequence for safety rails.
  • Startup delays are controlled internally in the LP873248-Q1 sequencer.
  • I2C can be used to read status registers and reset interrupts.
  • All PMIC devices in this system have dedicated I2C address so they can share the same I2C bus.
  • GPO signal from LP873248-Q1 act as SAF_RESET signal for the SoC. SFT_PWR_GD signal can be used for fault indication, or combined with the SAF_RESET signal (both outputs are open-drain).
Figure 2-3 Semidrive X9P/U RTC Power Block Diagram

Main features:

  • 5 V supplied from pre-regulator
  • VDD_RTC_1V8 supply starts as soon as supply voltage reaches TPS74501-Q1 UVLO rising threshold (1.33-V typ).
  • VDDIO_RTC_0V8 starts when VDD_RTC_1V8 has reached the target voltage and PG is set high.
  • When VDDIO_RTC_0V8 has reached the target voltage level the PG is set high. Additional RC delay is used for the RTC_RESET signal.