SNVAA65 March   2023 LM63610-Q1 , LM63615-Q1 , LM63625-Q1 , LM63635-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Inverting Buck-Boost Topology
    1. 1.1 Concept
    2. 1.2 Output Current Calculations
    3. 1.3 Voltage Range of Inverting Buck-Boost Configuration
  4. 2Design Considerations
    1. 2.1 Bypass Capacitor and Optional Schottky Diode
  5. 3External Components
    1. 3.1 Capacitor Selection
  6. 4Digital Pin Configurations
    1. 4.1 Optional Enable (EN) Level Shifter
    2. 4.2 Power-Good (PG) Pin
  7. 5Typical Performance
    1. 5.1 VOUT = -3.3 V, 2.1 MHz Typical Performance
    2. 5.2 VOUT = -3.3 V, 400 kHz Typical Performance
    3. 5.3 VOUT = -5 V, 2.1 MHz Typical Performance
    4. 5.4 VOUT = -5 V, 400 kHz Typical Performance
  8. 6Conclusion
  9. 7References

4.2 Power-Good (PG) Pin

Similar to EN, the power good flag needs to be level shifted if it is used for an inverting buck-boost application. The circuit shown in #ID-837BBF91-CCAA-4F15-A91A-B65AC4FA3E06 can be used to level shift the PGOOD logic as a signal that swings to zero volts. When using the circuit, the PGOOD pin needs to be rated for |VOUT|.

When the internal PGOOD switch turns off, the gate of the first external MOSFET is pulled to ground, causing the MOSFET to turn on. With the first MOSFET on, the gate of the second MOSFET is pulled to -VOUT, turning the second MOSFET off. With the second switch off, the PGOOD node is pulled to the logic voltage.

When the internal PGOOD switch turns on, the gate of the first external MOSFET is pulled to -VOUT, turning off the MOSFET. With the first external MOSFET off, the gate of the second external MOSFET is pulled to the logic voltage of the controller. This causes the second external MOSFET to turn on and pull the PGOOD node to ground. When selecting the external MOSFETs, they must have a VGS rating of at least |VOUT|.

Figure 4-2 PG Pin Level Shifter