The basics of how to use a buck converter in a fly-buck-boost topology are illustrated by Figure 1-1. The left side of this figure illustrates the standard buck, whereas the right side shows how a standard buck converter can be used in the fly-buck-boost topology.

To achieve this design, the buck converter is first converted into an inverting buck-boost topology. The needed modifications for that are shown in red. VOUT and GND label or symbol on the output of the buck converter needs to be interchanged as a first step. An additional bypass capacitor (Cbyp) is needed for bypassing the buck converter-IC U1 supply voltage. Schottky diode D3 avoids the possibility that U1 is overstressed by the charging current of Cbyp during start-up. Special care is required for the signals referred, directly, or through resistors or capacitors connected to ground in a normal buck converter. For example, for the GND-, FB-, EN-/UVLO-, PG-, RT- and VCC-pin of U1, the signals need to be referred in an inverting buck-boost to neg VOUT instead. The input voltage that can be applied to an inverting buck-boost converter is less than the input voltage that can be applied to the same buck converter. This relationship is because the GND-pin of the IC is connected to the negative output voltage Neg VOUT. Therefore, the input voltage across the converter-IC U1 is VIN + |Neg VOUT|.

As a next step, the inverting buck-boost is converted into the desired fly-buck-boost topology by adding the components and connections shown in green. Those connections are a second winding (L2) on the existing inductor (L1), a rectifying Schottky diode (D1), an output capacitor (C1), and the clamping Zener diode (D2). The two windings L1 and L2 preferably have the same number of turns, resulting in a coupled inductor with a 1:1 turns ratio. Such configuration of inductors is available as off-the-shelf product from the majority of inductor manufacturers. The energy stored during the ON-time of the converter by L1 releases during the OFF-time by L1 and L2 through the low-side FET of U1 and the Schottky diode D1 to the output capacitors C2 and C1. Because of the 1:1 turns ratio across the windings, L1 and L2 have the same voltage during the OFF-time leading to a good match of the non-regulated positive output voltage (Pos VOUT) to the well-regulated negative output voltage (Neg VOUT). The remaining tolerances of the Pos VOUT are due to the temperature- and load-dependent forward voltage drop of D1 at medium-to-maximum output current on the Pos VOUT. At very low output current on Pos VOUT there is a slight rise of that rail caused by the peak rectification of unavoidable spikes. The latter behavior is addressed by the clamping Zener diode D2, which has a Zener voltage slightly larger than the maximum nominal voltage to be expected as Pos VOUT.