Negative gate voltages are popular in many high-power systems to increase the FET immunity to false turn-on. A negative gate voltage creates more margin between the off-state voltage and the threshold voltage of the FET. This voltage margin allows the FET to tolerate more miller current injection without causing a shoot-through. Negative gate voltages are popular for IGBTs and SiC FETs; many SiCFET data sheets list a negative gate bias as a requirement.

GaN FETs do not require a negative gate bias but using one offers the same benefits as SiCFETs. The downside to a negative gate voltage is that it increases the negative voltage during the dead time, which increases overcharging and losses. Using methods such as a Miller clamp, rather than a negative bias, boosts Miller immunity without having overcharging issues.