SNVK008 April   2024 TPS7H4011-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Product Description
    2. 1.2 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Unbiased
      2. 2.3.2 Biased
    4. 2.4 Biased Test Configuration and Condition
  6. 3TI Characterization Test Results
    1. 3.1 TID Characterization Summary Results
    2. 3.2 Specification Compliance Matrix
      1. 3.2.1 Electrical Characteristics
  7. 4Applicable and Reference Documents
    1. 4.1 Applicable Documents
    2. 4.2 Reference Documents
  8.   A Appendix A: HDR Results Report at 100krad(Si)

3.2.1 Electrical Characteristics

Table 3-1 Electrical Characteristics
PARAMETERTEST CONDITIONSSUB-GROUPMINTYPMAXUNITTEST NUMBERS
POWER SUPPLIES AND CURRENTS
VUVLOR_PVINPVIN internal UVLO rising threshold1, 2, 33.23.43.6V14.1,14.7, 14.13, 14.19
VUVLOHYST_PVINPVIN internal UVLO hysteresis1, 2, 3425450500mV4.3, 14.9, 14.15, 14.21
VUVLOR_VINVIN internal UVLO rising threshold1, 2, 33.43.63.8V14.4, 14.10, 14.16, 14.22
VUVLOHYST_VINVIN internal UVLO hysteresis1, 2, 3140155170mV14.6, 14.12, 14.18, 14.24
ISHDN_VINVIN shutdown supply currentVEN = 0VVIN = 4.5V1, 2, 322.9mA12.1
VIN = 14V1, 2, 32312.16
ISHDN_PVINPVIN shutdown supply currentVEN = 0VPVIN = 4.5V1, 2, 32.63.5mA12.2
PVIN = 14V1, 2, 33.54.712.17
IQ_VINVIN operating quiescent current (non switching)VEN = 7V, VSENSE = 1V (3)1, 2, 32.65mA12.3, 12.8, 12.13, 12.18
ENABLE AND FAULT
VEN(rising)Enable rising threshold (turn-on)1, 2, 30.5550.610.655V15.3, 15.6, 15.9, 15.12
VEN(falling)Enable falling threshold (turn-off)1, 2, 30.460.510.55415.4, 15.7, 15.10, 15.13
tEN(delay)Enable propogation delayEN high to SW high, CSS = 22nF1, 2, 352100µs24.32, 24.72, 24.112, 24.152
IEN(LKG)Enable input leakage currentVEN = 7V1, 2, 3225nA15.1, 15.15
VFAULT(rising)FAULT threshold rising (turn-off)1, 2, 30.570.60.65V16.1, 16.5, 16.9, 16.13
VFAULT(falling)FAULT threshold falling (turn-on)1, 2, 30.470.50.5516.2,16.6, 16.10, 16.14
VFAULT(HYS)FAULT hysteresis voltage1, 2, 390100110mV16.3, 16.7, 16.11, 16.15
IFAULT(LKG)Fault input leakage currentVFAULT = 7V1, 2, 335µA16.4, 16.8, 16.12, 16.16
tFAULT(min)FAULT minimum pulse widthsee FAULT Minimum Pulse and Delay Duration9, 10, 110.41.4µs24.39, 24.79, 24.119, 24.159
tFAULT(delay)FAULT delay durationsee FAULT Minimum Pulse and Delay Duration9, 10, 11263144(1/fsw) s24.34, 24.36, 24.38,24.74, 24.76, 24.78, 24.114, 24.116, 24.118,24.154, 24.156, 24.158
VOLTAGE REFERENCE AND REMOTE SENSE
VREFInternal voltage reference (including error amplifier VIO)see Reference Voltage Measurement TA = –55℃30.5960.5990.603V
TA = 25℃10.5970.60.60317.3,17.11, 17.19, 17.27
TA = 125℃20.5960.5990.603
VREF(internal)Internal voltage reference (without error amplifier included)VREF(internal) = VSS_TR – VSNS-1, 2, 30.5940.60.606V17.1, 17.9, 17.17, 17.25
VBGBandgap voltage (voltage at the REFCAP pin)CREFCAP = 470nF1, 2, 31.1821.21.218V12.5,12.10, 12.15, 12.20
IVSNS+(LKG)VSNS+ input leakage current VSNS+ = 0.6V1, 2, 31030nA17.5, 17.13, 17.21, 17.29
IVSNS-VSNS- output current 1, 2, 381012µA17.4,17.12, 17.20,17.28
ERROR AMPLIFIER
VIOError amplifier input offset voltageVSENSE = 0.6V1, 2, 3–2.32.9mV17.2, 17.10, 17.18, 17.26
gmEAError amplifier transconductance–10μA < ICOMP < 10μA, VCOMP = 1V9, 10, 11100016002300µS18.1,18.4, 18.7, 18.10
EADCError amplifier DC gainVSENSE = 0.6V11500V/V
EAISRCError amplifier sourceVCOMP = 1V, 100mV input overdrive1, 2, 370125180µA18.2,18.5, 18.8, 18.11
EAISNKError amplifier sink7012518018.3, 18.6, 18.9, 18.12
EARoError amplifier output resistance7MΩ
EABWError amplifier bandwidth9MHz
gmpsPower stage transconductance,
18.3A (typ) current limit		IOUT = 12A,
ILIM = AVDD		TA = –55℃314.419.424.8S
TA = 25℃115.220.426.120.12, 20.46, 20.80, 20.114
TA = 125℃2162127
gmpsPower stage transconductance,
13.4A (typ) current limit		IOUT = 9A, 
RILIM_TOP = 49.9kΩ, 
RILIM_BOT = 100kΩ		TA = –55℃39.313.316.3S
TA = 25℃19.613.817.520.13, 20.47, 20.81, 20.115
TA = 125℃210.61418.1
gmpsPower stage transconductance,
18.3A (typ) current limit		VCOMP = 0.6V, ILIM = AVDD1, 2, 31822.928.3S20.18, 20.52,20.86, 20.120
gmpsPower stage transconductance,
13.4A (typ) current limit		VCOMP = 0.65V, RILIM_TOP = 49.9kΩ, 
RILIM_BOT = 100kΩ		1, 2, 31316.320.6S20.19, 20.53,20.87, 20.121
gmpsPower stage transconductance,
9A (typ) current limit		VCOMP = 0.7V, RILIM_TOP = 100kΩ, 
RILIM_BOT = 49.9kΩ		1, 2, 381114S20.20, 20.54, 20.88, 20.122
gmpsPower stage transconductance,
5.6A (typ) current limit		VCOMP = 0.75V, ILIM = GND1, 2, 34.67.29.2S20.21, 20.55, 20.89, 20.123
OVERCURRENT PROTECTION
IOC_HS1High-side switch current limit
threshold 1		RSHORT = 100mΩILIM = GND1, 2, 34.35.66.5A
ILIM = GND, post TID = 100krad(Si) 13.74.86.5

20.4, 20.38, 20.72, 20.106

RILIM_T = 100kΩ, 
RILIM_B = 49.9kΩ		1, 2, 37.2910.620.5,20.39, 20.73, 20.107
RILIM_T = 49.9kΩ,
RILIM_B = 100kΩ		1, 2, 311.213.41620.6,20.40, 20.74, 20.108
ILIM = AVDD1, 2, 315.818.321.820.7,20.41, 20.75,20.109
IOC_HS2High-side switch current limit
threshold 2		VIN = 12V,
RSHORT ≈ 4mΩ		ILIM = GND1, 2, 356.68.1A20.8,20.42, 20.76, 20.110
RILIM_T = 100kΩ, 
RILIM_B = 49.9kΩ		1, 2, 39.111.113.220.9 20.43, 20.77, 20.111
RILIM_T = 49.9kΩ,
RILIM_B = 100kΩ		1, 2, 314.11720.220.10 20.44,20.78,20.112 20.11, 20.45, 20.79,20.113
ILIM = AVDD1, 2, 319.123.928.2
IOC_LS(sink)Low-side switch sinking overcurrent thresholdTA = –55°C31.62.33.1A
TA = 25°C11.52.22.819.2,19.5, 19.8, 19.11
TA = 125°C21.422.4
IILIM(lkg)ILIM input leakage currentILIM = 7V1, 2, 3225nA15.2,15.16
COMPSHDNCOMP shutdown voltage1, 2, 31.71.92.1V22.1,22.7, 22.13,22.19
tCOMP(delay)COMP shutdown delay30µs
SOFT START AND TRACKING
tSSSoft start timeVSS_TR from 10% to 90%, VSNS- = GND,
VOUT(set) = 3.3V		CSS = 5.6nF9, 10, 111.5ms22.4,22.10, 22.16,22.22
CSS = 22nF9, 10, 114.75.87.322.5,22.11, 22.17,22.23
CSS = 100nF9, 10, 1124.722.6,22.12, 22.18,22.24
RSS(discharge)Soft start discharge pull-down resistor1, 2, 3200442700Ω22.2,22.8, 22.14,22.20
SSstartupMaximum voltage on SS before startup (5) 120mV22.3,22.9, 22.15,22.21
SLOPE COMPENSATION
SCSlope compensation with 18.3A (typ) current limitfSW = 100kHz,
ILIM = AVDD		RSC = 1.1MΩ–0.7A/µs
fSW = 500kHz,
ILIM = AVDD		RSC = 80.6kΩ–8.8
RSC = 196kΩ–4.2
RSC = 1.1MΩ–1.2
fSW = 1000kHz,
ILIM = AVDD		RSC = 80.6kΩ–10.5
RSC = 196kΩ–5.1
RSC = 1.1MΩ–2.1
Slope compensation with 13.4A (typ) current limitfSW = 500kHz,
RILIM_TOP = 49.9kΩ,
RILIM_BOT = 100kΩ		RSC = 196kΩ–3.2A/µs
Slope compensation with 9A (typ) current limitfSW = 500kHz,
RILIM_TOP = 100kΩ,
RILIM_BOT = 49.9kΩ		RSC = 196kΩ–2.4A/µs
Slope compensation with 5.6A (typ) current limitfSW = 500kHz,
ILIM = GND		RSC = 196kΩ–1.8A/µs
MINIMUM ON TIME AND DEAD TIME
ton(min)Minimum on time50% to 50% of VIN,
ISW = 2A		VIN = 4.5V9, 10, 11210235ns

24.31

VIN = 5V9, 10, 11213250

24.71

VIN = 12V9, 10, 11199250

24.111

VIN = 14V9, 10, 11199250

24.151

toff(min)Minimum off timeISW = 2A9, 10, 11306ns
tdeadDead time9, 10, 1170ns
SWITCHING FREQUENCY AND SYNCHRONIZATION
fSWRT programmed switching frequencyRRT = 511kΩ4, 5, 685100115kHz24.14, 24.15,24.54, 24.55, 24.94, 24.95, 24.134,24.135
RRT = 90.9kΩ4, 5, 645050055024.26, 24.27, 24.66, 24.67, 24.106,24.107, 24.146,24.147
RRT = 40.2kΩ4, 5, 68501000115024.28, 24.29,

24.68, 24.69, 24.108,24.109, 24.148,24.149

tSYNC_RSYNC1, SYNC2 out low-to-high rise time (10% to 90%)SYNCM = GND, Cload = 25pF,
see see SYNCx Rise and Fall Time		9, 10, 111021ns24.18, 24.19,24.58, 24.59,24.98, 24.99,24.138,24.139
tSYNC_FSYNC1, SYNC2 out high-to-low fall time (90% to 10%)SYNCM = GND, Cload = 25pF,
see SYNCx Rise and Fall Time		9, 10, 111021ns24.20, 24.21,24.60, 24.61,24.100,24.101,24.140,24.141
SYNCPH_2_1SYNC2 to SYNC1 rising edge phase shiftSYNCM = GND, see SYNC2 to SYNC1 Rising Edge Phase Shift9, 10, 11829098°24.17,24.57,24.97,24.137
tSYNC_DSYNC1 to SW delayNon-inverted SYNC1 input (SYNC2 = AVDD,
SYNCM = AVDD), see SYNC1 to SW Delay: Non-inverted Sync		VIN = 4.5V9, 10, 11140225350ns24.2
5V ≤ VIN ≤ 14V9, 10, 1112021027024.42, 24.82,24.122
VIN = 12V,
IOUT = 12A		9, 10, 11224
Inverted SYNC1 input
(SYNC2 = GND,
SYNCM = AVDD), see SYNC1 to SW Delay: Inverted Sync 		VIN = 4.5V9, 10, 11150256390ns24.3
5V ≤ VIN ≤ 14V9, 10, 1114024030024.43, 24.83,24.123
VIN = 12V,
IOUT = 12A		9, 10, 11246
SYNC1 output
(SYNCM = GND), see SYNC1 to SW Delay: SYNC1 Output		VIN = 4.5V9, 10, 11110180280ns24.16
5V ≤ VIN ≤ 14V9, 10, 119017525024.56, 24.96,24.136
VIN = 12V,
IOUT = 12A		9, 10, 11184
VSYNCx(OH)SYNC1, SYNC2 output highSYNCM = GND,
IOH = 2mA		4.5V ≤ VIN ≤ 5V1, 2, 3VIN–0.3V24.22, 24.23,24.62, 24.63
VIN > 5V1, 2, 34.555.224.102,24.103,24.142,24.143
VSYNCx(OL)SYNC1, SYNC2 output lowSYNCM = GND, IOL = 2mA1, 2, 30.4V24.24, 24.25,24.64, 24.65,24.104,24.105,24.144,24.145
VSYNC1(IH)SYNC1 input high thresholdSYNCM = AVDD 1, 2, 31.7V24.4,24.44, 24.84,24.124
VSYNC1(IL)SYNC1 input low thresholdSYNCM = AVDD1, 2, 30.724.5,24.45, 24.85,24.125
fSYNCSYNC1 input frequency rangeSYNCM = AVDD4, 5, 61001000kHz24.1,24.8, 24.9,24.41, 24.48,24.49, 24.81,24.88, 24.89,24.121,24.128,24.129
DSYNCSYNC1 input duty cycle rangeSYNCM = AVDD, external clock duty cycle4, 5, 640%60%24.10, 24.11,24.50, 24.51,24.90, 24.91,24.130,24.131
tCLK_E_IExternal clock to internal clock detection timeSYNCM = AVDD, RT populated9, 10, 1125(1/fsw) s24.12, 24.52,24.92, 24.132
tCLK_I_EInternal clock to external clock detection timeSYNCM = AVDD, RT populated9, 10, 1112(1/fsw) s24.13, 24.53,24.93, 24.133
POWER GOOD AND THERMAL SHUTDOWN
PWRGDLOW_F%PWRGD falling threshold (fault), lowThreshold for PWRGD (VSENSE as percent of VREF), VSNS- = 0VVSENSE falling1, 2, 390%92%94%23.2,23.9, 23.16,23.23
PWRGDLOW_R%PWRGD rising threshold (good), lowVSENSE rising1, 2, 393%95%97%23.3,23.10, 23.17,23.24
PWRGDHIGH_R%PWRGD rising threshold (fault), highVSENSE rising1, 2, 3106%108%110%23.4,23.11, 23.18,23.25
PWRGDHIGH_F%PWRGD falling threshold (good), highVSENSE falling1, 2, 3103%105%107%23.5,23.12, 23.19,23.26
IPWRGD(LKG)Output high leakageVSENSE = VREF, VPWRGD = 7V1, 2, 350500nA23.6,23.13, 23.20,23.27
VPWRGD(OL)Power good output lowIPWRGD(SINK) = 0mA to 2mA1, 2, 3250300mV23.7,23.14, 23.21,23.28
VINMIN_PWRGDMinimum VIN for valid PWRGD outputMeasured when VPWRGD ≤ 0.5V at 100μA1, 2, 312V23.1
TSD(enter)Thermal shutdown enter temperature170°C
TSD(exit)Thermal shutdown exit temperature135
TSD(HYS)Thermal shutdown hysteresis35
MOSFET
RDS_ON_HSHigh-side switch resistance at
IHS = 12A		PVIN = VIN = 4.5VTA = –55℃33853mΩ
TA = 25℃1506120.2,20.3
TA = 125℃26479
PVIN = VIN = 5VTA = –55℃33650
TA = 25℃1486020.36, 20.37
TA = 125℃26273
PVIN = VIN = 12VTA = –55℃33445
TA = 25℃1455320.70, 20.71
TA = 125℃25967
PVIN = VIN = 14VTA = –55℃33445
TA = 25℃1455320.104,20.105
TA = 125℃25967
RDS_ON_LSLow-side switch resistance at
ILS = 12A (6)		PVIN = VIN = 4.5VTA = –55℃32540mΩ
TA = 25℃1355121.2,21.3
TA = 125℃25161
PVIN = VIN = 5VTA = –55℃32335
TA = 25℃1334521.8,21.9
TA = 125℃24856
PVIN = VIN = 12VTA = –55℃32332
TA = 25℃1334221.14, 21.15
TA = 125℃24755
PVIN = VIN = 14VTA = –55℃32332
TA = 25℃1334221.20, 21.21
TA = 125℃24755