SNVK010 Radiation & reliability report

SNVK010 August 2024 TPS7H4011-SP

3.2 Data Sheet Electrical Parameter Characteristics

Over 4.5V ≤ VIN ≤ 14V, PVIN = VIN, VSNS- = 0V, open loop configuration, IOUT = 0A, TA = 25°C, unless otherwise noted

Table 3-1 Data Sheet Electrical Parameter Characteristics

PARAMETER		TEST CONDITIONS		SUB-GROUP	MIN	TYP	MAX	UNIT	TEST NUMBERS
POWER SUPPLIES AND CURRENTS
V_{UVLOR_PVIN}	PVIN internal UVLO rising threshold			1, 2, 3	3.2	3.4	3.6	V	14.1,14.7, 14.13, 14.19
V_{UVLOHYST_PVIN}	PVIN internal UVLO hysteresis			1, 2, 3	425	450	500	mV	14.3, 14.9, 14.15, 14.21
V_{UVLOR_VIN}	VIN internal UVLO rising threshold			1, 2, 3	3.4	3.6	3.8	V	14.4, 14.10, 14.16, 14.22
V_{UVLOHYST_VIN}	VIN internal UVLO hysteresis			1, 2, 3	140	155	170	mV	14.6, 14.12, 14.18, 14.24
I_{SHDN_VIN}	VIN shutdown supply current	V_EN = 0V	VIN = 4.5V	1, 2, 3		2	2.9	mA	12.1
I_{SHDN_VIN}	VIN shutdown supply current	V_EN = 0V	VIN = 14V	1, 2, 3		2	3	mA	12.16
I_{SHDN_PVIN}	PVIN shutdown supply current	V_EN = 0V	PVIN = 4.5V	1, 2, 3		2.6	3.5	mA	12.2
I_{SHDN_PVIN}	PVIN shutdown supply current	V_EN = 0V	PVIN = 14V	1, 2, 3		3.5	4.7	mA	12.17
I_{Q_VIN}	VIN operating quiescent current (non switching)	V_EN = 7V, VSENSE = 1V		1, 2, 3		2.6	5	mA	12.3, 12.8, 12.13, 12.18
ENABLE AND FAULT
V_EN(rising)	Enable rising threshold (turn-on)			1, 2, 3	0.555	0.61	0.655	V	15.3, 15.6, 15.9, 15.12
V_EN(falling)	Enable falling threshold (turn-off)			1, 2, 3	0.455	0.51	0.554	V	15.4, 15.7, 15.10, 15.13
t_EN(delay)	Enable propogation delay	EN high to SW high, SS pin open		1, 2, 3		52	100	µs	24.32, 24.72, 24.112, 24.152
I_EN(LKG)	Enable input leakage current	V_EN = 7V		1, 2, 3		2	100	nA	15.1, 15.15
V_{FAULT(rising)}	FAULT threshold rising (turn-off)			1, 2, 3	0.555	0.6	0.635	V	16.1, 16.5, 16.9, 16.13
V_{FAULT(falling)}	FAULT threshold falling (turn-on)			1, 2, 3	0.455	0.5	0.535	V	16.2,16.6, 16.10, 16.14
V_FAULT(HYS)	FAULT hysteresis voltage			1, 2, 3	90	100	110	mV	16.3, 16.7, 16.11, 16.15
I_FAULT(LKG)	Fault input leakage current	V_FAULT = 7V		1, 2, 3		3	5	µA	16.4, 16.8, 16.12, 16.16
t_FAULT(min)	FAULT minimum puls width			9, 10, 11	0.4		1.4	µs	24.39, 24.79, 24.119, 24.159
t_FAULT(delay)	FAULT delay duration			9, 10, 11	26	31	44	(1/f_sw) s	24.34, 24.36, 24.38, 24.74, 24.76, 24.78, 24.114, 24.116, 24.118, 24.154, 24.156, 24.158
VOLTAGE REFERENCE AND REMOTE SENSE
V_REF	Internal voltage reference (including error amplifier V_IO)	See data sheet for more info	T_A = –55℃	3	0.595	0.598	0.603	V
			T_A = 25℃	1	0.596	0.6	0.603		17.3,17.11, 17.19, 17.27
			T_A = 125℃	2	0.596	0.599	0.603
V_{REF(internal)}	Internal voltage reference (without error amplifier included)	V_{REF(internal)} = V_{SS_TR} – VSNS-		1, 2, 3	0.593	0.6	0.606	V	17.1, 17.9, 17.17, 17.25
V_BG	Bandgap voltage (voltage at the REFCAP pin)	C_REFCAP = 470nF		1, 2, 3	1.184	1.2	1.222	V	12.5,12.10, 12.15, 12.20
I_VSNS+(LKG)	VSNS+ input leakage current	VSNS+ = 0.6V		1, 2, 3		10	30	nA	17.5, 17.13, 17.21, 17.29
I_VSNS-	VSNS- output current			1, 2, 3	8	10	12	µA	17.4, 17.12, 17.20, 17.28
ERROR AMPLIFIER
V_IO	Error amplifier input offset voltage	VSENSE = 0.6V		1, 2, 3	–2.3		2.9	mV	17.2, 17.10, 17.18, 17.26
g_mEA	Error amplifier transconductance	–10μA < I_COMP < 10μA, V_COMP = 1V	T_A = –55℃	11	1400	2050	2700	µS
			T_A = 25℃	9	1200	1650	2100		18.1,18.4, 18.7, 18.10
			T_A = 125℃	10	1000	1250	1500
EA_DC	Error amplifier DC gain	VSENSE = 0.6V				11500		V/V
EA_ISRC	Error amplifier source	V_COMP = 1V, 100mV input overdrive		1, 2, 3	90	125	200	µA	18.2,18.5, 18.8, 18.11
EA_ISNK	Error amplifier sink	V_COMP = 1V, 100mV input overdrive		1, 2, 3	90	125	200	µA	18.3, 18.6, 18.9, 18.12
EA_Ro	Error amplifier output resistance					7		MΩ
EA_BW	Error amplifier bandwidth					9		MHz
g_mps	Power stage transconductance, 18.3A (typ) current limit	I_OUT = 12, ILM = AVDD	T_A = –55℃	3	14.4	19.4	24.8	S
			T_A = 25°C	1	15.2	20.4	26.1		20.12, 20.46, 20.80, 20.114
			T_A = 125°C	2	16	21	27
g_mps	Power stage transconductance, 13.4A (typ) current limit	I_OUT = 9A, R_{ILM_TOP} = 49.9kΩ, R_{ILIM_BOT} = 100kΩ	T_A = –55℃	3	9.3	13.3	17	S
			T_A = 25°C	1	9.6	13.8	17.5		20.13, 20.47, 20.81, 20.115
			T_A = 125°C	2	9.7	14	18.1
g_mps	Power stage transconductance, 18.3A (typ) current limit	V_COMP = 0.6V, ILIM = AVDD		1, 2, 3	17.8	22.4	28.3	S	20.18, 20.52, 20.86, 20.120
g_mps	Power stage transconductance, 13.4A (typ) current limit	V_COMP = 0.65V, R_{ILIM_TOP} =49.9kΩ, R_{ILIM_BOT} = 100kΩ		1, 2, 3	12.8	16.1	20.6	S	20.19, 20.53, 20.87, 20.121
g_mps	Power stage transconductance, 9A (typ) current limit	V_COMP = 0.65V, R_{ILIM_TOP} =100kΩ, R_{ILIM_BOT} = 49.9kΩ		1, 2, 3	8	11	15.5	S	20.20, 20.54, 20.88, 20.122
g_mps	Power stage transconductance, 5.6A (typ) current limit	V_COMP = 0.75V, ILIM = GND		1, 2, 3	4.6	7.2	9.2	S	20.21, 20.55, 20.89, 20.123
OVERCURRENT PROTECTION
I_{OC_HS1}	High-side switch current limit threshold 1	R_SHORT = 100mΩ	ILIM = GND	1, 2, 3		5.6	7.5	A
			R_{ILIM_T} = 100kΩ, R_{ILIM_B} = 49.9kΩ	1, 2, 3		9	11.9		20.5, 20.39, 20.73, 20.107
			R_{ILIM_T} = 49.9kΩ, R_{ILIM_B} = 100kΩ	1, 2, 3		13.4	17.8		20.10, 20.44, 20.78, 20.112
			ILIM = AVDD	1, 2, 3		18.3	24.9		20.7, 20.41, 20.75, 20.109
I_{OC_HS2}	High-side switch current limit threshold 2	VIN = 12V, R_SHORT ≈ 4mΩ	ILIM = GND			6.6		A	20.8, 20.42, 20.76, 20.110
			R_{ILIM_T} = 100kΩ, R_{ILIM_B} = 49.9kΩ			11.1			20.9, 20.43, 20.77, 20.111
			R_{ILIM_T} = 49.9kΩ, R_{ILIM_B} = 100kΩ			17			20.10, 20.44, 20.78, 20.112
			ILIM = AVDD			23.9			20.11, 20.45, 20.79, 20.113
I_{OC_LS(sink)}	Low-side switch sinking overcurrent threshold	T_A = –55°C		3	1.6	2.3	3.6	A
		T_A = 25°C		1	1.5	2.2	3.3		19.2,19.5, 19.8, 19.11
		T_A = 125°C		2	1.4	2	2.8
I_ILIM(lkg)	ILIM input leakage current	ILIM = 7V		1, 2, 3		2	100	nA	15.2,15.16
COMP_SHDN	COMP shutdown voltage			1, 2, 3	1.7	1.9	2.1	V	22.1,22.7, 22.13,22.19
t_COMP(delay)	COMP shutdown delay					30		µs
SOFT START AND TRACKING
t_SS	Soft start time	V_{SS_TR} from 10% to 90%, VSNS- = GND, V_OUT(set) = 3.3V	C_SS = 5.6nF			1.5		ms	22.4,22.10, 22.16,22.22
			C_SS = 22nF	9, 10, 11	4.7	5.8	7.3		22.5,22.11, 22.17,22.23
			C_SS = 100nF			24.7			22.6,22.12, 22.18,22.24
R_{SS(discharge)}	Soft start discharge pull-down resistor			1, 2, 3	200	442	700	Ω	22.2,22.8, 22.14,22.20
SS_startup	Maximum voltage on SS before startup (5)					20		mV	22.3,22.9, 22.15,22.21
SLOPE COMPENSATION
SC	Slope compensation with 18.3A (typ) current limit	f_SW= 100kHz, ILIM = AVDD	R_SC = 1.1MΩ			–0.7		A/µs
		f_SW = 500kHz, ILIM = AVDD	R_SC = 80.6kΩ			–8.8
			R_SC = 196kΩ			–4.2
			R_SC = 1.1MΩ			–1.2
		f_SW = 1000kHz, ILIM = AVDD	R_SC = 80.6kΩ			–10.5
			R_SC = 196kΩ			–5.1
			R_SC = 1.1MΩ			–2.1
	Slope compensation with 13.4A (typ) current limit	f_SW = 500kHz, R_{ILIM_TOP} = 49.9kΩ, R_{ILIM_BOT} = 100kΩ	R_SC = 196kΩ			–3.2		A/µs
	Slope compensation with 9A (typ) current limit	f_SW = 500kHz, R_{ILIM_TOP} = 100kΩ, R_{ILIM_BOT} = 49.9kΩ	R_SC = 196kΩ			–2.4		A/µs
	Slope compensation with 5.6A (typ) current limit	f_SW = 500kHz, ILIM = GND	R_SC = 196kΩ			–1.8		A/µs
MINIMUM ON TIME AND DEAD TIME
t_on(min)	Minimum on time	50% to 50% of VIN, I_SW = 2A	VIN = 4.5V	9, 10, 11		210	235	ns	24.31
			VIN = 5V	9, 10, 11		213	250		24.71
			VIN = 12V	9, 10, 11		199	250		24.111
			VIN = 14V	9, 10, 11		199	250		24.151
t_off(min)	Minimum off time	I_SW = 2A				306		ns
t_dead	Dead time					70		ns	24.4, 24.8, 24.12, 24.16
SWITCHING FREQUENCY AND SYNCHRONIZATION
f_SW	RT programmed switching frequency	R_RT = 511kΩ		4, 5, 6	90	100	120	kHz	24.14, 24.15, 24.54, 24.55, 24.94, 24.95, 24.134, 24.135
		R_RT = 90.9kΩ		4, 5, 6	450	500	550		24.26, 24.27, 24.66, 24.67, 24.106, 24.107, 24.146, 24.147
		R_RT = 40.2kΩ	VIN = 4.5V	4, 5, 6	850	1000	1150		24.28, 24.29
		R_RT = 40.2kΩ	5V ≤ VIN ≤ 14V	4, 5, 6	870	1000	1170		24.68, 24.69, 24.108, 24.109, 24.148, 24.149
t_{SYNC_R}	SYNC1 out low-to-high rise time (10% to 90%)	Cload = 25pF, see see SYNCx Rise and Fall Time		9, 10, 11		10	21	ns	24.18, 24.19, 24.58, 24.59, 24.98, 24.99, 24.138, 24.139
t_{SYNC_F}	SYNC1 out high-to-low fall time (90% to 10%)	Cload = 25pF, see SYNCx Rise and Fall Time		9, 10, 11		10	21	ns	24.20, 24.21, 24.60, 24.61, 24.100, 24.101, 24.140, 24.141
SYNC_{PH_2_1}	SYNC2 to SYNC1 rising edge phase shift	SYNCM = GND		9, 10, 11	82	90	98	^o	24.17, 24.57, 24.97, 24.137
t_{SYNC_D}	SYNC1 to SW delay	Non-inverted SYNC1 input (SYNC2 = AVDD, SYNCM = AVDD)	VIN = 4.5V	9, 10, 11	140	225	350	ns	24.2
			5V ≤ VIN ≤ 14V	9, 10, 11	120	210	270		24.42, 24.82,24.122
			VIN = 12V, IOUT = 12A			224
		Inverted SYNC1 input (SYNC2 = GND, SYNCM = AVDD)	VIN = 4.5V	9, 10, 11	150	256	390	ns	24.3
			5V ≤ VIN ≤ 14V	9, 10, 11	140	240	300		24.43, 24.83,24.123
			VIN = 12V, IOUT = 12A			246
		SYNC1 output (SYNCM = GND)	VIN = 4.5V	9, 10, 11	110	180	280	ns	24.16
			5V ≤ VIN ≤ 14V	9, 10, 11	90	175	250		24.56, 24.96,24.136
			VIN = 12V, IOUT = 12A			184
V_SYNCx(OH)	SYNC1, SYNC2 output high	SNYCM = GND, I_OH = 2mA	4.5V ≤ VIN ≤ 5V	1, 2, 3	VIN–0.3			V	24.22, 24.23,24.62, 24.63
V_SYNCx(OH)	SYNC1, SYNC2 output high	SNYCM = GND, I_OH = 2mA	VIN > 5V	1, 2, 3	4.5	5	5.2	V	24.102,24.103,24.142,24.143
V_SYNCx(OL)	SYNC1, SYNC2 output low	SYNCM = GND, I_OL = 2mA		1, 2, 3			0.4	V	24.24, 24.25,24.64, 24.65,24.104,24.105,24.144,24.145
V_SYNC1(IH)	SYNC1 input high threshold	SYNCM = AVDD		1, 2, 3			1.7	V	24.4,24.44, 24.84,24.124
V_SYNC1(IL)	SYNC1 input low threshold	SYNCM = AVDD		1, 2, 3	0.7			V	24.5,24.45, 24.85,24.125
f_SYNC	SYNC1 input frequency range	SYNCM = AVDD		4, 5, 6	100		1000	kHz	24.1,24.8, 24.9,24.41, 24.48,24.49, 24.81,24.88, 24.89,24.121,24.128,24.129
D_SYNC	SYNC1 input duty cycle range	SYNCM = AVDD, external clock duty cycle		4, 5, 6	40%		60%		24.10, 24.11,24.50, 24.51,24.90, 24.91,24.130,24.131
t_{CLK_E_I}	External clock to internal clock detection time	SYNCM = AVDD, RT populated		9, 10, 11		2	5	(1/f_sw) s	24.12, 24.52,24.92, 24.132
t_{CLK_I_E}	Internal clock to external clock detection time	SYNCM = AVDD, RT populated		9, 10, 11		1	2	(1/f_sw) s	24.13, 24.53,24.93, 24.133
POWER GOOD AND THERMAL SHUTDOWN
PWRGD_{LOW_F%}	PWRGD falling threshold (fault), low	Threshold for PWRGD ( VSENSE as percent of V_REF), VSNS- = 0V	VSENSE falling	1, 2, 3	90%	92%	95%		23.2,23.9, 23.16,23.23
PWRGD_{LOW_R%}	PWRGD rising threshold (good), low		VSENSE rising	1, 2, 3	93%	95%	98%		23.3,23.10, 23.17,23.24
PWRGD_{HIGH_R%}	PWRGD rising threshold (fault), high		VSENSE rising	1, 2, 3	106%	108%	112%		23.4,23.11, 23.18,23.25
PWRGD_{HIGH_F%}	PWRGD falling threshold (good), high		VSENSE falling	1, 2, 3	103%	105%	109%		23.5,23.12, 23.19,23.26
I_PWRGD(LKG)	Output high leakage	VSENSE = V_REF, V_PWRGD = 7V		1, 2, 3		50	500	nA	23.6,23.13, 23.20,23.27
V_PWRGD_(OL)	Power good output low	I_PWRGD_(SINK) = 0mA to 2mA		1, 2, 3		250	300	mV	23.7,23.14, 23.21,23.28
VIN_{MIN_PWRGD}	Minimum VIN for valid PWRGD output	Measured when V_PWRGD ≤ 0.5V at 100μA		1, 2, 3		1	2	V	23.1
T_SD(enter)	Thermal shutdown enter temperature					170		°C
T_SD(exit)	Thermal shutdown exit temperature					135
T_SD(HYS)	Thermal shutdown hysteresis					35
MOSFET
R_{DS_ON_HS}	High-side switch resistance at I_HS = 12A (lead length ≈ 3mm)	PVIN = VIN = 4.5V	T_A = –55℃	3		38	53	mΩ
			T_A = 25℃	1		50	61		20.2,20.3
			T_A = 125℃	2		64	79
		PVIN = VIN = 5V	T_A = –55℃	3		36	50
			T_A = 25℃	1		48	60		20.36, 20.37
			T_A = 125℃	2		62	73
		PVIN = VIN = 12V	T_A = –55℃	3		34	45
			T_A = 25℃	1		45	53		20.70, 20.71
			T_A = 125℃	2		59	67
		PVIN = VIN = 14V	T_A = –55℃	3		34	45
			T_A = 25℃	1		45	53		20.104,20.105
			T_A = 125℃	2		59	67
R_{DS_ON_LS}	Low-side switch resistance at I_LS = 12A (lead length ≈ 3mm)	PVIN = VIN = 4.5V	T_A = –55℃	3		25	40	mΩ
			T_A = 25℃	1		35	51		21.2,21.3
			T_A = 125℃	2		51	61
		PVIN = VIN = 5V	T_A = –55℃	3		23	35
			T_A = 25℃	1		33	45		21.8,21.9
			T_A = 125℃	2		48	56
		PVIN = VIN = 12V	T_A = –55℃	3		23	32
			T_A = 25℃	1		33	42		21.14, 21.15
			T_A = 125℃	2		47	55
		PVIN = VIN = 14V	T_A = –55℃	3		23	32
			T_A = 25℃	1		33	42		21.20, 21.21
			T_A = 125℃	2		47	55