7.3.1.1 LED Driver Current Control

LED driver output current can be programmed with I²C register from 0 mA up to 25.5 mA. Current setting resolution is 100 μA (8-bit control).

7.3.1.2 Controlling LED Driver Output PWM

PWM can be controlled by either with program execution engines (1, 2 and 3) or via I²C registers (02h for B, 03h for G, 04h for R and 0Eh for W).

Control of LED driver output PWM selection is managed with 2 bits for each LED output from register 70h. The Table 3 describes the selection options. With these bits for example all LED outputs can be controlled from one program execution engine.

Figure 14. Controlling LED Outputs

The LED driver PWM control with 8-bit I²C register is defined in Table 2.

If the LED driver outputs are controlled with engines, the engine adjusts the PWM according to the program code. However, when the engine mode bits are set to ‘11’, the engine is set to direct mode. In direct mode the PWM controls of engines comes:

• Engine 1 PWM control comes from B PWM I²C register (02h)
• Engine 2 PWM control comes from G PWM I²C register (03h)
• Engine 3 PWM control comes from R PWM I²C register (04h)

When the engine mode bits are set to '11' along with the LED PWM Output selection bits, it is possible to control all LED outputs from one I²C register.

Table 4. ENABLE Register (00h)

Table 5. CONFIG Register (08h)

7.3.3.1 Program Execution Engine States

Engine program execution is controlled from ENABLE register (00h). There are four different states for each engine, and these states are described in Table 6.

7.3.3.2 Program Execution Engine Operation Modes

Operation modes are defined in register address 01h. Each engine (1, 2, 3) operation mode can be configured separately. Mode registers are synchronized to a 32-kHz clock. Delay between consecutive I²C writes to OP_MODE register (01h) need to be longer than 153 μs (typ).

7.3.3.3 Program Execution Engine Program Counter (PC)

Program execution engine Program Counter tells the current program code command, which engine is executing. By setting the program counter value before starting the engine execution, user can set the starting point of the program execution.

7.3.3.4 Program Execution Engine Programming Commands

The LP5562 has three independent programmable engines (1, 2, 3). Trigger connections between engines are common for all engines. All engines have own program memory sections for storing LED lighting patterns. Brightness control and patterns are done with 8-bit PWM control (256 steps) to get accurate and smooth color control. Program execution is timed with a 32.7-kHz clock. This clock can be generated internally or an external 32-kHz clock can be connected to the CLK_32K pin. Using an external clock enables synchronization of LED timing to this clock rather than an internal clock. Selection of the clock is made with address 08H bits INT_CLK_EN and CLK_DET_EN. See External Clock for details. Supported commands are listed in Table 9.

7.3.3.4.1 Ramp/Wait

The ramp command generates a PWM ramp starting from current value. At each ramp step the output is incremented by one. Time for one step is defined with Prescale and Step time bits. Minimum time for one step is 0.49 ms and maximum time is 63 × 15.6 ms = 1 second/step, so it is possible to program very fast and also very slow ramps. Increment value defines how many steps are taken in one command. Number of actual steps is Increment + 1. Maximum value is 127d, which corresponds to half of full-scale (128 steps). If during ramp command PWM reaches minimum/maximum (0/255) ramp command will be executed to the end and PWM will stay at minimum/maximum. This enables the ramp command to be used as combined ramp and wait command in a single instruction.

The ramp command can be used as wait instruction when increment is zero.

Setting register 00h bit LOG_EN sets the scale as either linear to logarithmic. When LOG_EN = 0, linear scale is used, and when LOG_EN = 1, logarithmic scale is used. By using logarithmic scale the visual effect of the ramp command seems linear to the eye.

Table 10. Ramp/Wait Command

Ramp/Wait command
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Pre- scale	Step time						Sign	Increment

Table 11. Ramp/Wait Command Bits

NAME	VALUE(d)	DESCRIPTION
Prescale	0	Divides master clock (32.768 Hz) by 16 = 2048 Hz, 0.49 ms cycle time
	1	Divides master clock (32.768 Hz) by 512 = 64 Hz, 15.6 ms cycle time
Step time	1-63	One ramp increment done in (step time) x (clock after prescale) Note: 0 means set PMW command.
Sign	0	Increase PWM output
	1	Decrease PWM output
Increment	0-127	The number of steps is Increment + 1. Note: 0 is a wait instruction.

For example, if following parameters are used for ramp:

• Prescale = 1 ≥ cycle time = 15.6 ms
• Step time = 2 ≥ time = 15.6 ms × 2 = 31.2 ms
• Sign = 0 ≥ rising ramp Increment = 4 ≥ 5 cycles

Ramp command will be: 0100 0010 0000 0100b = 4204h

If current PWM value is 3, and the first command is as described above, the next command is a ramp with otherwise same the parameters, but with Sign = 1 (Command = 4284h), the result will be like in the following figure:

Figure 16. Example of 2 Sequential Ramp Commands

7.3.3.5 Program Load and Execution Example

• Start up device and configure device to SRAM write mode
  • Supply 3.6V to VDD
  • Supply 1.8V to EN
  • Wait 1 ms
  • Generate 32 kHz clock to CLK_32K pin
  • Write to address 00h 0100 0000b (enable device)
  • Wait 500 μs (startup delay)
  • Write to address 01h 0001 0000b (configure engine 1 into 'Load program to SRAM' mode)
• Program load to SRAM
  • Write to address 10h 0000 0011b (1st ramp command 8MSB)
  • Write to address 11h 0111 1111b (1st ramp command 8 LSB)
  • Write to address 12h 0100 1101b (1st wait command 8 MSB)
  • Write to address 13h 0000 0000b (1st wait command 8 LSB)
  • Write to address 14h 0000 0011b (2nd ramp command 8 MSB)
  • Write to address 15h 1111 1111b (2nd ramp command 8 LSB)
  • Write to address 16h 0110 0000b (2nd wait command 8 MSB)
  • Write to address 17h 0000 0000b (2nd wait command 8 LSB)
• Enable Power Save and use external 32 kHz clock
  • Write to address 08h 0010 0000b (enable powersave, use external clock)
• Run program
  • Write to address 01h 0010 0000b (Configure LED controller operation mode to "Run program" in engine 1)
  • Write to address 00h 0110 0000b (Configure program execution mode from "Hold" to "Run" in engine 1)

The LP5562 will generate a 1100 ms long LED pattern which will be repeated infinitely. The LED pattern is illustrated in the figure below.

Figure 17. LED Lighting Pattern and Code for Program Load and Execution Example

Table 20. Engine Operation Mode and Power Save

Table 21. Engine Commands and Power Save

Table 22. CONFIG Register (08h)

Table 23. SRAM Memory Registers

7.5.2.1 Interface Bus Overview

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL).

7.5.2.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 20. Data Validity

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

Figure 21. Acknowledge Signal

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 22. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

7.5.2.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

7.5.2.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

7.5.2.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP5562 operates as a slave device with the 7-bit address. LP5562 I²C address is pin selectable from four different choices. If 8-bit address is used for programming, the 8th bit is 1 for read and 0 for write. Table 24 shows the 8-bit I²C addresses.

Before any data is transmitted, the master transmits the address of the slave being addressed.

The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 23. I²C chip address

7.5.2.6 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes the control register address will be incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

7.5.2.7 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

7.5.2.8 Register Read/Write Format

Figure 24. Register Write Format

When a read function is to be accomplished, a write function must precede the read function, as show in the Read Cycle waveform.

Figure 25. Register Read Format

w = write (SDA = 0)

r = read (SDA = 1)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address

Table 27. Enable Register Field Descriptions

Table 28. OP Mode Register Field Descriptions

Table 29. B_PWM Register Field Descriptions

Table 30. G_PWM Register Field Descriptions

Table 31. R_PWM Register Field Descriptions

Table 32. B_CURRENT Register Field Descriptions

Table 33. G_CURRENT Register Field Descriptions

Table 34. R_CURRENT Register Field Descriptions

Table 35. CONFIG Register Field Descriptions

Table 36. Engine 1 PC Register Field Descriptions

Table 37. Engine 2 PC Register Field Descriptions

Table 38. Engine 3 PC Register Field Descriptions

Table 39. STATUS/INTERRUPT Register Field Descriptions

Table 40. RESET Register Field Descriptions

Table 41. W_PWM Register Field Descriptions

Table 42. W_CURRENT Register Field Descriptions

Table 43. LED Map Register Field Descriptions