8.3.1.1 Operation

The boost DC/DC converters generate 7-V to 28-V boost output voltage from a 2.7-V to 20-V boost input voltage (input voltage must be lower than V_BOOST). The maximum boost output voltage can be set digitally by pre-configuring EPROM memory (VMAX field).

The converter is a magnetic switching PWM mode DC/DC boost converter with a current limit. It uses CPM (current programmed mode) control, where the inductor current is measured and controlled with the feedback. During start-up, the soft-start function reduces the peak inductor current. Figure 20 shows the boost block diagram.

Figure 20. Boost Converter Functional Block Diagram

Both boost converters are operating at 180° phase shift to reduce current spikes from the input rail and EMI.

8.3.1.2 Protection

Three different protection schemes are implemented:

1. Overvoltage protection, limits the maximum output voltage:
   • Overvoltage protection limit changes dynamically based on output voltage setting. If the boost voltage is over 1.6 V higher than the adaptive control set value, the boost will stop switching.
   • Keeps the output below breakdown voltage. The output voltage control limits the boost maximum voltage to 18...28 V (EPROM programmable).
   • Prevents boost operation if battery voltage is much higher than desired output.
2. Overcurrent protection, limits the maximum inductor current to 3.1 A (EPROM programmable).
3. Duty cycle limiting.

8.3.1.3 Setting Boost Switching Frequency

The LP8555 boost converter switching frequency can be set by pre-configuring EPROM memory with the choice of boost frequency (BFREQ field). Table 1 summarizes setting of the switching frequency.

8.3.1.4 Adaptive Boost Output Voltage Control

The boost converters operate in adaptive voltage control mode in typical application. The voltages at the LED terminals is monitored by the control loop. It raises the boost voltage when the measured voltage of ANY of the LED strings in a bank falls below the voltage threshold of its corresponding LOW comparator. If the headrooms of ALL of the LED strings in a bank are above the voltage threshold of their corresponding MID comparator, then the boost voltage is lowered. Both banks have independent boost voltage control to save power in case of Vf mismatch between LED strings.

The initial boost voltage is configured with the VINIT field. The VMAX field sets the maximum boost voltage. When an LED terminal is open, the monitored voltage will never have enough headroom and the adaptive mode control loop will keep raising the boost voltage. The VMAX field allows the boost voltage to be limited to stay under the voltage rating of the external components.

Figure 21. Boost Adaptive Control Principle for Bank A Boost Converter With Phase Shifted Outputs

8.3.1.5 EMI Reduction

The LP8555 features three EMI reduction schemes.

First scheme, Programmable Slew Rate Control, uses a combination of four drivers for boost switch. Enabling all four drivers allows boost switch on/off transition times to be the shortest. On the other hand, enabling just one driver allows boost switch on/off transition times to be the longest. The longer the transition times, the lower the switching noise on the SW node. It should also be noted that the shortest transition times bring the best efficiency as the switching losses are the lowest. Same controls effect both boost converters.

The second EMI reduction scheme is the Spread Spectrum Scheme which deliberately spreads the frequency content of the boost switching waveform, which inherently has a narrow bandwidth, makes the switching waveform's noise spectrum bandwidth wider and ultimately reduces its EMI spectral density.

The third feature for reducing EMI is Phase Shifted Clocking mode, where boost converters’ clocks are operating 180° phase shifted. This prevents boost switches switching on at the same time when operating in PWM mode. This reduces input rail load transient spikes caused by boost inductor current and gate driver currents.

Figure 22. Boost Converter EMI Reduction Schemes

8.3.2.1 PWM Input Duty Measurement

When using PWM input for brightness control the input PWM duty cycle is measured as described in following diagram and the brightness is controlled based on the result. When changing the brightness it must be noted that the measurement cycle is from rising edge to next rising edge and brightness change must be done accordingly (time from rising to rising edge is constant (=cycle time) and falling edge defines the brightness).

Figure 23. PWM Input Duty Cycle Measurement

8.3.2.2 BRTMODE = 00

With BRTMODE = 00, the LED output current is controlled by the PWM input duty cycle. The PWM detector block measures the duty cycle at the PWM/INT terminal and uses it to generate a PWM-based brightness code. Before the output is generated, the code goes through the curve Shaper block. Then the code goes into the Hybrid PWM and Current Dimming block which determines the range of the PWM and Current control. The outcome of the Hybrid PWM and Current Dimming block is Current and/or up to 6 PWM output signals.

Figure 24. BRTMODE = 00 Brightness Control

8.3.2.3 BRTMODE = 01

With BRTMODE = 01, the LED output current is controlled by the BRTHI/BRTLO registers. Before the output is generated the BRTHI/BRTLO registers-based brightness code goes through the Curve Shaper block. Then the code goes into the Hybrid PWM and Current Dimming block which determines the range of the PWM and Current control. The outcome of the Hybrid PWM and Current Dimming block is Current and/or up to 6 PWM output signals.

Figure 25. BRTMODE = 01 Brightness Control

8.3.2.4 BRTMODE = 10

With BRTMODE = 10, the LED output current is controlled by PWM input duty cycle and the BRTHI/BRTLO registers. The PWM detector block measures the duty cycle at the PWM/INT terminal and uses it to generate PWM-based brightness code. Before the code is multiplied with the BRTHI/BRTLO registers-based brightness code, it goes through the Curve Shaper block. After the multiplication, the resulting code goes into the Hybrid PWM and Current Dimming block which determines the range of the PWM and Current control. The outcome of the Hybrid PWM and Current Dimming block is Current and/or up to 6 PWM output signals.

Figure 26. BRTMODE = 10 Brightness Control

8.3.2.5 BRTMODE = 11

With BRTMODE = 11, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO registers. The PWM detector block measures the duty cycle at the PWM/INT terminal and uses it to generate PWM-based brightness code. In this mode, the BRTHI/BRTLO registers-based brightness code goes through the Curve Shaper block before it is multiplied with the PWM input duty cycle-based brightness code. After the multiplication, the resulting code goes into the Hybrid PWM and Current Dimming block which determines the range of the PWM and Current control. The outcome of the Hybrid PWM and Current dimming block is Current and/or up to 6 PWM output signals.

Figure 27. BRTMODE = 11 Brightness Control

8.3.2.6 Hybrid PWM and Current Dimming Control

Hybrid PWM and Current Dimming control combines PWM dimming and LED current-dimming control methods. With this dimming control, it is possible to achieve better optical efficiency from the LEDs compared to pure PWM control while still achieving smooth and accurate control and low brightness levels. The switch point from current-to-PWM control is set with THRESHOLD EPROM field, available settings are Pure PWM dimming (THRESHOLD = 111b), 25% switch point (THRESHOLD = 101b) and Pure Current Dimming (THRESHOLD = 000b). 25% setting allows good compromise between good matching of the LEDs brightness/white point at low brightness and good optical efficiency.

Figure 28.

Figure 30.

Figure 29.

8.3.2.7 Setting PWM Dimming Frequency

The LP8555 LED PWM dimming frequency can be set either by an external resistor (PFSET = 1 selection), R_FSET, or by pre-configuring EPROM memory with the choice of PWM dimming frequency (PFREQ field). Table 2 summarizes setting of the PWM dimming frequency. Setting the PWM dimming frequency using an external resistor is separately shown in Table 3.

8.3.2.8 Setting Full-Scale LED Current

The LP8555 full-scale LED current can be set either by an external resistor R_ISET (ISET = 1 selection), or by pre-configuring EPROM memory with the choice of full-scale LED current (MAXCURR field, ISET = 0). This register can be also written with I²C before turning on backlight. Table 4 summarizes setting of the full-scale LED current.

8.3.2.9 Phase-Shift PWM Scheme

The Phase-Shift PWM Scheme (PSPWM) allows delaying of the time when each LED current sink is active. When the LED current sinks are not activated simultaneously, the peak load current from the boost output is greatly decreased during PWM dimming. This reduces the ripple seen on the boost output and allows smaller output capacitors to be used. Reduced ripple also reduces the output ceramic capacitor audible ringing. The PSPWM scheme also increases the load frequency seen on the boost output by up to six times and therefore transfers the possible audible noise to the frequencies outside of the audible range.

The phase difference between each active driver is automatically determined and is 360º / number of active drivers in a bank.

Figure 31. Phase Shifting Example With All 12 Channels Active. (Note: Bank A And Bank B are in the Same Phase.)

8.3.4.1 Start-up With PWM Input Brightness Control Mode (BRTMODE = 00b)

When VDD and EN/VDDIO are above min operational value the LP8555 enters start-up mode. During start-up mode the LDO is started, and EPROM values are read. I²C is available after the start-up sequence has ended.

In standby mode the device waits for the ON bit to go high to start the boost start-up sequence. In standby mode PWM input duty cycle measurement is active.

Once the ON bit is set to 1 (it can be also programmed to 1 by default in EPROM, and no I²C write is then needed for entering active mode), boost is started, and device enters active mode with brightness set by PWM input duty cycle. If no brightness is set, the backlight stays off until two PWM pulses are received in the PWM input, or if PWM input is set high for more than 1/75 Hz time. Boost starts initially to the level programmed in EPROM, and after backlight is turned on the adaptive control adjusts the voltage to get to the minimal headroom voltage.

8.3.4.2 Shutdown With PWM Input Brightness Control Mode (BRTMODE = 00b)

The backlight can be turned off by setting PWM input low or by writing the ON bit low. After a 1/75Hz timeout period in the PWM input, the backlight slopes down (if slope is enabled), and boost is returned to the initial voltage level programmed to the EPROM. If the backlight is shut down with the ON bit, it shuts down immediately even if slopes are enabled and boost turns off as well. To enter standby mode where boost is disabled and the power consumption is minimal, the ON bit must be written to 0. If PWMSB bit has been programmed to 1, then the LP8555 enters standby mode when PWM input has been low for more than 50 ms even if the ON bit is high.

The device shuts down completely by setting EN/VDDIO and/or VDD to low state.

Figure 33. Start-up and Shutdown with PWM Input Control, ON Bit = 0 (BRTMODE = 00b)

Figure 34. Start-up and Shutdown with PWM Input Control, ON Bit = 1 (BRTMODE = 00b)

8.3.4.3 Start-up With I²C Brightness Control Mode (BRTMODE = 01b)

When VDD and EN/VDDIO are above min operational value, the LP8555 enters start-up mode. During start-up mode the LDO is started, and EPROM values are read. I²C is available after the start-up sequence has ended.

In standby mode the device waits for the ON bit to go high to start the boost start-up sequence. In standby mode I²C is active, and brightness / other registers can be written.

Once the ON bit is set to 1 (it can be also programmed to 1 by default in EPROM and no I²C write is then needed for entering active mode), boost is started, and device enters active mode with brightness set by I²C brightness registers. If no brightness is set, the backlight stays off until brightness value is written to the I²C register(s). Boost starts initially to the level programmed in EPROM and, after backlight is turned on, the adaptive control adjusts the voltage to get to the minimal headroom voltage.

8.3.4.4 Shutdown With I²C Brightness Control Mode (BRTMODE = 01b)

The backlight can be turned off by setting the ON bit low, or by writing brightness to 0. The backlight shuts down immediately if the ON bit is written low even if slope is enabled. If the backlight is turned off by writing brightness to 0, brightness control does slope (if enabled), and the boost is returned to the initial voltage level programmed to EPROM. To enter standby mode where boost is disabled and the power consumption is minimal, the ON bit must be written to 0.

The device shuts down completely by setting EN/VDDIO and/or VDD to low state.

Figure 35. Start-up And Shutdown With I²C Brightness Control Mode (BRTMODE = 01b)

8.3.4.5 Start-up with I²C + PWM Input Brightness Control Mode (BRTMODE = 10 or 11b)

When VDD and EN/VDDIO are above min operational value, the LP8555 enters start-up mode. During start-up mode the LDO is started, and EPROM values are read. I²C is available after the start-up sequence has ended.

In standby mode the device waits for the ON bit to go high to start the boost start-up sequence. In standby mode I²C registers can be written and PWM input duty cycle measurement is active.

Once the ON bit is set to 1 (it can be also programmed to 1 by default in EPROM and no I²C write is then needed for entering active mode), boost is started, and device enters active mode with brightness set by PWM input duty cycle multiplied by I²C brightness register value. If no brightness is set, the backlight stays off until I²C brightness register receives value and two PWM pulses are received in the PWM input, or if PWM input is set high for more than 1/75 Hz time. Boost starts initially to the level programmed in EPROM and after backlight is turned on, the adaptive control adjusts the voltage to get to the minimal headroom voltage.

8.3.4.6 Shutdown with I²C + PWM Input Brightness Control Mode (BRTMODE = 10 or 11b)

The backlight can be turned off by setting the ON bit low, or by setting brightness to 0 either by PWM input (same 1/75 Hz timeout applies here as in PWM input control mode) or by I²C brightness register writes. The backlight shuts down immediately if the ON bit is written low even if slope is enabled. If the backlight is turned off by setting brightness to 0, brightness control does slope (if enabled, depending on which input is used – see brightness control modes for details), and the boost is returned to the initial voltage level programmed to EPROM. To enter standby mode where boost is disabled and the power consumption is minimal, the ON bit must be written to 0.

The device shuts down completely by setting EN/VDDIO and/or VDD to low state.

Figure 36. Start-up and Shutdown with I²C + PWM Input Brightness Control (BRTMODE = 01b)

8.3.6.1 LED Short Detection

Voltages at the individual current sinks are constantly monitored for the LED SHORT fault. This fault may occur when some LEDs in a string are electrically bypassed making that LED string shorter than the other LED strings. The reduced forward voltage causes the current sink attached to that string to have a higher headroom voltage than the other current sinks. When the headroom voltage is higher than the fault comparator threshold (configured with the OV field in the LEDEN register) that current sink is disabled and the PWM phasing is automatically adjusted. The fault comparator threshold may be configured for 1 V, 2 V, 3 V or 4 V.

8.3.6.2 LED Open Detection

Each current sink is also monitored for an LED OPEN condition. The condition is set when the headroom voltage on one or more current sinks is below the LOW comparator threshold and the boost voltage is at the maximum. This fault condition may be caused by one or more OPEN LED strings or by one or more current sinks shorted to GND.

The AUTO bit of the CONFIG register determines how the LP8555 responds to an LED OPEN condition. If the CONFIG.AUTO bit is set to 1, the LP8555 will automatically adjust the phasing to remove the current sink with the LED OPEN condition. In this case the condition is normal and indicates an unpopulated LED string. If the CONFIG.AUTO bit is set to 0, the LP8555 will immediately shut down the backlight whenever an LED OPEN condition is detected on any enabled LED drivers. The backlight will not turn on again (regardless of the COMMAND.ON bit) until the STATUS register is read.

8.3.6.3 Undervoltage Detection

The LP8555 continuously monitors the voltage on the VDD terminal. When the VDD voltage drops below 2.5 V the backlight will be immediately shut down, and the UVLO bit will be set in the STATUS register. The backlight will automatically start again when the voltage has increased above 2.5 V + 50 mV hysteresis. Hysteresis is implemented to avoid continuously triggering undervoltage.

8.3.6.4 Thermal Shutdown

If the internal temperature reaches 150°C, the LP8555 will immediately shut down the backlight to protect it from damage. The TSD bit will also be set in the STATUS register. The device will re-activate the backlight again when the internal temperature drops below 137°C (typ).

8.3.6.5 Boost Overcurrent Protection

The LP8555 will automatically limit boost current to 3.1 A (EPROM programmable). When the 3.1-A limit is reached the BST_OCP bit is set in the STATUS register.

8.3.6.6 Boost Overvoltage Protection

The LP8555 will automatically limit boost voltage to VBOOST_MAX+1.6 V. When the limit is reached the BST_OVP bit is set in the STATUS register. It is possible to set the limit to four threshold levels programmable via EPROM bits.

8.3.6.7 Boost Undervoltage Protection

The LP8555 can detect when the boost voltage is below VBOOST – 2.5 V for longer than 6ms. When the threshold is reached the BST_UV bit is set in the STATUS register.

8.3.7.1 Interface Bus Overview

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol use a two-wire interface for bi-directional communications between the IC’s connected to the bus. The two interface lines are the Serial Data Line (FSET/SDA), and the Serial Clock Line (ISET/SCL). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (ISET/SCL). The LP8555 is always a slave device.

See the LP8555EVM User Guide for full register map details and programming considerations.

8.3.7.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 37. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

Figure 38. Start And Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 39. Start And Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

8.3.7.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

8.3.7.4 “Acknowledge After Every Byte” Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

8.3.7.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP8555 operates as a slave device with 7-bit address combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write, and 59h for read in an 8-bit format.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 40. I²C Slave Address

8.3.7.6 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes, the control register address will be incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

8.3.7.7 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

<> Data from master; [ ] Data from slave.

Figure 41. Register Write Format

Figure 42. Register Read Format