SNVS857 Data sheet

SNVS857 February 2014 LP8555

PRODUCTION DATA.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VDD	Voltage on VDD	–0.3	22	V
VLDO	Voltage on VLDO	–0.3	6
V(PWM/INT, EN/VDDIO/ FSET/SDA, ISET/SCL)	Voltage on logic terminals	–0.3	6
V(SW_A, SW_B, LEDxy, FB_x)	Voltage on analog terminals	–0.3	31
P_D	Continuous Power Dissipation ⁽³⁾		Internally limited
T_A	Operating ambient temperature range ⁽⁵⁾	–40	85	°C
T_J	Maximum operating junction temperature ⁽⁵⁾	–40	125
T_soldering	Note ⁽⁴⁾

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

		MIN	MAX	UNIT
T_STORAGE	Storage temp range	–65	150	°C
V_HBM	Human body model (HBM) voltage⁽¹⁾		2000	V
V_CDM	Charged device model (CDM) ⁽²⁾		250	V

(1) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Terminals listed as 2 kV may actually have higher performance.

(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance

7.3 Recommended Operating Conditions⁽¹⁾⁽²⁾

Over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
VDD – Voltage on VDD	2.7	20	V
VLDO – Voltage on VLDO	2.7	5.5
V (EN/VDDIO) – Supply voltage for digital I/O	1.7	5.5
V (PWM/INT, FSET/SDA, ISET/SCL) – Voltage on logic terminals	0	5.5
V (SW_A, SW_B, LEDxy, FB_x)	0	28

7.4 Thermal Information

Over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC⁽¹⁾		DSBGA (36 TERMINALS)	UNIT
θ_JA	Junction-to-ambient thermal resistance (θ_JA) ⁽⁶⁾	76.2	°C/W
θ_JC	Junction-to-case (top) thermal resistance	0.3	°C/W
θ_JB	Junction-to-board thermal resistance	16.3	°C/W
Ψ_JT	Junction-to-top characterization parameter	1.8	°C/W
Ψ_JB	Junction-to-board characterization parameter	16.3	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics⁽²⁾⁽⁷⁾

Limits apply over the full ambient temperature range –40°C ≤ T_A ≤ 85°C. Unless otherwise specified: VDD = 3.6 V, EN/VDDIO = 1.8 V, L1 = L2 = 6.8 µH, C_{IN_A} = C_{IN_B} = 10 µF, C_{OUT_A} = C_{OUT_B} = 10 µF, C_VLDO = 10 µF, C_VDD = 1 µF.⁽⁸⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_IN	Shutdown supply current	EN = L and PWM/INT = L			1	µA
	Standby supply current	EN = H and PWM/INT = L, ON bit = 0		19	30	µA
	Normal mode supply current	EN = H, ON bit = 1, no current going through LED outputs		4.2		mA
f_OSC	Internal oscillator frequency accuracy		-7%		7%
T_TSD	Thermal shutdown threshold			150		°C
T_{TSD_hyst}	Thermal shutdown hysteresis			13		°C
t_START-UP	Start-up time⁽⁹⁾			5	7	ms
BOOST CONVERTER (Applies for both boost converters)
V_{BST_MIN}	Minimum output voltage			7		V
V_{BST_MAX}	Maximum output voltage	VMAX = 00 VMAX = 01 VMAX = 10 VMAX = 11		18 22 25 28		V
I_MAX	SW FET current limit		2.7	3.1	3.5	A
R_NMOS	NMOS switch-ON resistance	I_SW = 0.5 A		0.16		Ω
I_LOAD	Continuous load current	VBATT = 3 V, VOUT = 26.6 V. Typical application.		180		mA
ƒ_SW	Switching frequency	BFREQ = 0 BFREQ = 1		500 1000		kHz
ƒ_{SW_ACCURACY}	Boost oscillator accuracy		–7%		7%
V_{OVP_THR}	Overvoltage protection voltage threshold			V_{BST_MAX} +1.6 V		V
V_OUT/V_IN	Conversion ratio	No load, BFREQ = 1	1.3		10
ΔV_SW/t_off-on	SW node voltage slew rate during OFF-to-ON transition	Load current 120 mA. Boost slew rate set to fastest (SRON = 00b).		12.5		V/ns
ΔV_SW/t_on-off	SW node voltage slew rate during ON-to-OFF transition			19.5		V/ns
ƒ_MOD	Modulation frequency (percentage of the SW frequency)	FMOD_DIV = 00 FMOD_DIV = 01 FMOD_DIV = 10 FMOD_DIV = 11		0.47% 0.27% 0.17% 0.12%
CURRENT SINKS
I_LEAKAGE	Leakage current	Outputs LEDA1...LEDB6, V_LEDxx = 28 V			1	µA
I_MAX	Maximum sink current LEDA1...B6			50		mA
I_OUT	Output current accuracy⁽¹⁰⁾	Output current set to 23 mA. Current scale set to 23 mA. PWM = 100%	–4%		4%
I_MATCH	Matching ⁽¹⁰⁾			1%	5%
ƒ_{LED_PWM}	LED switching frequency	PFREQ = 000b PFREQ = 111b		4.9 39.1		kHz
V_SAT	Saturation voltage ⁽¹¹⁾	Output current set to 23 mA		200	260	mV
V_SAT	Saturation voltage ⁽¹¹⁾	Output current set to 30 mA		250	340	mV
PWM INTERFACE CHARACTERISTICS
ƒ_PWM	PWM input frequency		75		50000	Hz
t_{MIN_ON}	Minimum pulse ON time			100		ns
t_{MIN_OFF}	Minimum pulse OFF time			100		ns
t_start-up	Turn-on delay from standby to backlight on	PWM input active, ON bit written high			7	ms
t_STBY	Turn-off delay	PWM input low time before entering standby mode (if PWMSB = 1)		52		ms
PWM_RES	PWM input resolution	ƒ_IN < 2.4 kHz ƒ_IN < 4.8 kHz ƒ_IN < 9.6 kHz ƒ_IN < 19.5 kHz ƒ_IN < 25 kHz ƒ_IN < 50 kHz		12 12 11 10 9 8		bits
UNDERVOLTAGE PROTECTION
V_UVLO	VDD UVLO threshold voltage	VDD falling		2.5		V
V_UVLO	VDD UVLO threshold voltage	VDD rising		2.6		V
LOGIC INTERFACE
Logic Input EN/VDDIO
V_EN/VDDIO	Supply voltage range		1.7		5.5	V
I_I	Input current			20		µA
Logic Input PWM/INT, FSET/SDA, ISET/SCL
V_IL	Input low level				0.3 x EN/VDDIO	V
V_IH	Input high level		0.7 x EN/VDDIO			V
I_I	Input current, VIO = 1.7 V to 5.5 V		-1.0		1.0	µA
Logic Output FSET/SDA, PWM/INT
V_OL	Output low level	I_PULL-UP = 3 mA		0.3	0.4	V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device a these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND terminals.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J = 150°C (typ.) and disengages at T_J = 137°C (typ.).

(4) For detailed soldering specifications and information, please refer to Application Note AN1112.

(5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be degraded. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125ºC), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the following equation: T_A-MAX = T_J-MAX-OP – (θ_JA × P_D-MAX).

(6) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

(7) Min and Max limits are specified by design, test, or statistical analysis.

(8) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics

(9) Start-up time is measured from the moment the ON bit is set high to the moment when backlight is enabled.

(10) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUTA1 to OUTB6), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED current sinks were characterized with 1 V headroom voltage. Note that some manufacturers have different definitions in use.

(11) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.6 I²C Serial Bus Timing Parameters (FSET/SDA, ISET/SCL)

		MIN	MAX	UNIT
f_SCL	Clock Frequency		400	kHz
1	Hold Time (repeated) START Condition	0.6		μs
2	Clock Low Time	1.3		μs
3	Clock High Time	600		ns
4	Setup Time for a Repeated START Condition	600		ns
5	Data Hold Time	50		ns
6	Data Setup Time	100		ns
7	Rise Time of SDA and SCL	20+0.1xC_b	300	ns
8	Fall Time of SDA and SCL	15+0.1xC_b	300	ns
9	Set-up Time for STOP condition	600		ns
10	Bus Free Time between a STOP and a START Condition	1.3		μs
C_b	Capacitive Load Parameter for Each Bus Line. Load of One Picofarad Corresponds to One Nanosecond.	10	200	ns
t_response	Delay from EN/VDDIO rising to I²C bus active		1	ms

Figure 1. I²C Timing Parameters

7.7 Typical Characteristics

Measured at room temperature unless otherwise noted. Maximum LED current set to 23 mA per string. DC-DC Efficiency is defined as P_OUT/P_IN, where P_OUT is total output power measured from boost output(s). LED Drive Efficiency is defined as P_LED/P_IN , where P_LED is actual power consumed in LEDs.