SNVSA38 November 2014 LM3281
PRODUCTION DATA.
Optimal LM3281 performance is realized when two important layout considerations are observed. TI-provided layout guidance in this section illustrates best practices, and a customer layout review with the TI applications team will ensure best performance is achieved.
Minimize inductance in the path between LM3281 COUT capacitor and the load bypass capacitors CLOAD1 and CLOAD2 for best performance. Total power path inductance from the LM3281 output to the load (including vias and traces) should target < 1 nH and must not exceed 2 nH.
Minimize inductance between LM3281 pins (VIN, GND) and the LM3281 input bypass capacitor CIN for best performance. The LM3281 device and CIN capacitor should be placed to permit shortest possible top-metal routing for these connections.
Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads which can result in erratic or degraded performance of the converter. By its very nature, any switching converter generates electrical noise, and the circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3281, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following general guidelines are offered to help mitigate EMI and facilitate good layout design.
Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in Texas Instruments Application Note 1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package should be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light (in the red and infrared range) shining on the package's exposed die edges.