SNVSAA7B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External Components Selection
            1. 9.2.1.2.1.1 Input Capacitors
              1. 9.2.1.2.1.1.1 Input Capacitor Selection
            2. 9.2.1.2.1.2 Output Inductors and Capacitors Selection
              1. 9.2.1.2.1.2.1 Inductor Selection
              2. 9.2.1.2.1.2.2 Output Capacitor Selection
          2. 9.2.1.2.2 Setting the Output Voltage
            1. 9.2.1.2.2.1 FB for Adjustable Versions
          3. 9.2.1.2.3 VCC
          4. 9.2.1.2.4 BIAS
          5. 9.2.1.2.5 CBOOT
          6. 9.2.1.2.6 Maximum Ambient Temperature
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Adjustable Output
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.4 Current Limit

The LM53625/35-Q1 incorporates valley current limit for normal overloads and for short-circuit protection. In addition, the low-side switch is also protected from excessive negative current when the device is in FPWM mode. Finally, a high-side peak-current limit is employed for protection of the top NMOS FET.

During overloads the low-side current limit, IL-LS (see Section 7.5), determines the maximum load current that the LM53625/35-Q1 can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall below IL-LS before the next turnon cycle, then that cycle is skipped, and the low-side FET is left on until the current falls below IL-LS. This is somewhat different than the more typical peak current limit, and results in Equation 1 for the maximum load current.

Equation 1. GUID-0BC53C77-3577-4BF0-9DBD-E6FE5949AF2B-low.gif

The LM53625/35-Q1 uses two current limits, which allow use of smaller inductors than systems utilizing a single current limit. A coarse high side or peak current limit is provided to protect against faults and saturated inductors. A precision valley current limit prevents excessive average output current from the buck converter of the LM53625/35-Q1. A new switching cycle is not initiated until inductor current drops below the valley current limit. This scheme allows use of inductors with saturation current rated less than twice the rated operating current of the LM53625/35-Q1.

If the converter keeps triggering valley current limit for more than about 64 clock cycles, the device turns off both high and low side switches for approximately 5.5 ms (see TW in Section 7.7. If the overload is still present after the hiccup time, another 64 cycles is counted, and the process is repeated. If the current limit is not tripped for two consecutive clock cycles, the counter is reset. Figure 8-5 shows the inductor current with a hard short on the output. The hiccup time allows the inductor current to fall to zero, resetting the inductor volt-second balance. This is the method used for short-circuit protection and keeps the power dissipation low during a fault. Of course the output current is greatly reduced in this condition (see Section 7.8. A typical short-circuit transient and recovery is shown in Figure 8-6.

GUID-6090FBC3-51DC-4C13-82CC-9D4C886B8633-low.pngFigure 8-5 Inductor Current Bursts in Short Circuit
GUID-E2FAFEB7-EDED-4394-A5C7-ECBF211E29A3-low.gifFigure 8-6 Short-Circuit Transient and Recovery

The high-side current limit trips when the peak inductor current reaches IL-HS (see Section 7.5). This is a cycle-by-cycle current limit and does not produce any frequency or current foldback. It is meant to protect the high-side MOSFET from excessive current. Under some conditions, such as high input voltage, this current limit may trip before the low-side protection. The peak value of this current limit varies with duty cycle.

In FPWM mode, the inductor current is allowed to go negative. Should this current exceed INEG, the low side switch is turned off until the next clock cycle. This is used to protect the low-side switch from excessive negative current. When the device is in AUTO mode, the negative current limit is increased to about IZC (about 0 A). This allows the device to operate in DCM.

The LM53625/35-Q1 response to a short circuit is: Peak current limit prevents excessive peak current while valley current limit prevents excessive average inductor current. After a small number of cycles of valley current limit triggers, hiccup mode is activated.