11.1 Layout Guidelines
Figure 76 shows a layout recommendation for the LP8863-Q1 used to illustrate the principles of good layout. This layout can be adapted to the actual application layout if and where possible. It is important that all boost components are close to each other and to the chip; the high-current traces must be wide enough. VDD must be as noise-free as possible. Place a VDD bypass capacitor near the VDD and GND pins and ground it to a low-noise ground. A charge-pump capacitor, boost input capacitors, and boost output capacitors must be connected to PGND. Place the charge-pump capacitors close to the device. The main points to guide the PCB layout design:
- Current loops need to be minimized:
- For low frequency the minimal current loop can be achieved by placing the boost components as close as possible to each other. Input and output capacitor grounds need to be close to each other to minimize current loop size.
- Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents follow the route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route.
- For high frequency the copper area capacitance must be taken into account. For example, the copper area for the drain of boost nMOSFET is a tradeoff between capacitance and the cooling capacity of the components.
- GND plane must be intact under the high-current-boost traces to provide shortest possible return path and smallest possible current loops for high frequencies.
- Current loops when the boost switch is conducting and not conducting must be in the same direction in optimal case.
- Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the inductor 180° changes current direction.
- Use separate power and noise-free grounds. PGND is used for boost converter return current. Use a low-noise ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the GND pins of the LP8863-Q1 device itself.
- Route boost output voltage (VOUT) to LEDs from output capacitors not straight from the diode cathode.
- A small bypass capacitor (TI recommends a 39-pF capacitor) must be placed close to the FB pin to suppress high frequency noise
- VDD line must be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it is grounded to noise-free ground.
- Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by the shortest way to boost a switch-current-sensing resistor. This capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.
- Input and output capacitors need low-impedence grounding (wide traces with many vias to PGND plane).
- If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working ideally.
- Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable under certain load conditions. DC bias characteristics should be obtained from the component manufacturer; DC bias is not taken into account on component tolerance. TI recommends X5R/X7R capacitors.