SNVSAJ6D July   2016  – December 2017 LM5141-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Synchronization
      5. 7.3.5  Frequency Dithering (Spread Spectrum)
      6. 7.3.6  Enable
      7. 7.3.7  Power Good
      8. 7.3.8  Output Voltage
        1. 7.3.8.1 Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
      13. 7.3.13 Hiccup Mode Current Limiting
      14. 7.3.14 Standby Mode
      15. 7.3.15 Soft Start
      16. 7.3.16 Diode Emulation
      17. 7.3.17 High- and Low-Side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Inductor Calculation
        3. 8.2.2.3 Current Sense Resistor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 Input Filter
          1. 8.2.2.5.1 EMI Filter Design
          2. 8.2.2.5.2 MOSFET Selection
          3. 8.2.2.5.3 Driver Slew-Rate Control
          4. 8.2.2.5.4 Frequency Dithering
        6. 8.2.2.6 Control Loop
          1. 8.2.2.6.1 Feedback Compensator
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Procedure
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8.2.2.6.1 Feedback Compensator

A type II compensator using an transconductance error amplifier (EA), Gm, is shown in Figure 35. The dominant pole of the EA open-loop gain is set by the EA output resistance, RAMP, and effective bandwidth-limiting capacitance, CO, as follows:

Equation 52. LM5141-Q1 equation_55_snvsaj6.gif

The EA high frequency pole is neglected in the above expression. The compensator transfer function from output voltage to COMP, including the gain contribution from the feedback resistor divider network is:

Equation 53. LM5141-Q1 equation_56_snvsaj6.gif
Equation 54. LM5141-Q1 equation_57_snvsaj6.gif

where

Equation 55. LM5141-Q1 equation_58_snvsaj6.gif

Which simplifies to:

Equation 56. LM5141-Q1 equation_59_snvsaj6.gif
LM5141-Q1 transconductance_amplifier_snvsaj6.gifFigure 35. Transconductance Amplifier
Equation 57. LM5141-Q1 equation_60_snvsaj6.gif
Equation 58. LM5141-Q1 equation_61_snvsaj6.gif
Equation 59. LM5141-Q1 equation_62_snvsaj6.gif

Typically RCOMP << RAMP and CCOMP >> (CHF + CO) so the approximations are valid.

where

VREF is the feedback voltage reference (1.2 V)

Gm is the error amplifier gain transconductance (1200 µs)

RAMP is the error amplifier output impedance (2.5 MΩ)

The error amplifier compensation components create a pole at the origin, a zero, and a high frequency pole.

The procedure for choosing compensation components for a stable closed loop is: