SNVSAQ5B November   2018  – May 2022 UCC27282

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Input Stages and Interlock
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.4 Device Functional Modes

When the device is enabled, the device operates in normal mode and UVLO mode. See Section 7.3.2 for more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is dependent on the states of the EN, HI and LI pins. The output HO and LO will be low if input state is floating.

Table 7-3 Input/Output Logic in Normal Mode of Operation
ENHILIHO (1)LO (2)
LHHLL
LHLL
HLLL
LLLL
HHHLL
LHLH
HLHL
LLLL
HFloatingLLL
FloatingHLH
LFloatingLL
HFloatingHL
FloatingFloatingFloatingLL
(1) HO is measured with respect to HS
(2) LO is measured with respect to VSS