SNVSAQ6D November   2016  – August 2021 LM5170-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.16.2 Nominal Circuit Breaker Function

If the failure detection function is enabled, which also implies the circuit breaker being controlled by the LM5170-Q1, the LM5170-Q1 will perform a MOSFET failure detection during start-up. The detection starts after the UVLO is pulled higher than 2.5 V and VCC above 8.5 V. The detection operation lasts for 2 to 3 ms. During the detection, the LM5170-Q1 checks the high-side and low-side MOSFETs of both channels as well as the circuit breaker MOSFETs to see if any of them has drain-to-source shorted. If no failure is detected, a 330-µA current source at the BRKG pin is turned on to charge up the breaker MOSFET gates. When the BRKG to BRKS voltage rises above 8.5 V, the LM5170-Q1 enters standby mode, waiting for the EN1 and EN2 commands to operate in power delivery mode. The voltage across BRKG and BRKS is internally clamped to 12 V, preventing overvoltage stress on the breaker MOSFET gates.

If a failure of any MOSFET is detected, the LM5170-Q1 immediately pulls the nFAULT pin low, and keeps the LM5170-Q1 in a latched shutdown mode, thereby preventing catastrophic failure.

The nFAULT pin can also be externally pulled low during normal operation and the LM5170-Q1 immediately turns off the circuit breaker and stays in a latched shutdown. There is a 2-µs glitch filter at the nFAULT pin to prevent errant shutdown by possible noises at the nFAULT pin.

To release the nFAULT shutdown latch, it requires the UVLO pin to be externally forced below 1.25 V, or VCC is below 8 V.

Figure 8-15 and Figure 8-16 show two ways to use the circuit breaker function. A TVS is recommended to prevent surge voltage when the circuit breaker is turned off during operation.

The BRKG 330-µA current source is powered by the VIN pin, or the HV-Port. Therefore, the differential voltage between the HV-Port and LV-Port should be greater than 10 V to ensure that BRKG to BRKS voltage can establish > 8.5 V and allow the LM5170-Q1 to enter power delivery mode. The BRKG to BRKS voltage is internally clamped to 12 V if the differential voltage of the two ports is greater.

The load dump transient at the LV-Port may raise the rail voltage and reduce the differential voltage of the two ports to below 10 V. To maintain the circuit breaker to be closed during the transient, TI recommends adding a 1-nF to 10-nF capacitor across BRKG and BRKS to hold the gate voltage during the transient.

Note that the BRKG 330-µA current source will always be turned on once the LM5170 starts up. If the failure detection mode is deactivated, the LM5170-Q1 will also skip checking the BRKG to BRKS votlage condition. Therefore, the circuit breaker can still be controlled by the LM5170-Q1 even if the failure detection is deactivated. If the steady-state differential voltage between the HV-Port and LV-Port is less than 10 V during power up, TI does not recommend the user to activate the failure detection function. Also, if the differential voltage is less than 8 V, TI recommends not to use the circuit breaker function of the LM5170-Q1 at all.

GUID-810EBA1F-FEFA-478E-B05C-FD19F5293D7D-low.gifFigure 8-15 Controlling Dual-Channel Circuit Breaker for MOSFET Failure Protection
GUID-4860CD03-51CB-4D14-8891-604CE578FD57-low.gifFigure 8-16 Controlling System Level Circuit Breaker for MOSFET Failure Protection
GUID-3050568E-407B-476F-96B3-9093212E75B7-low.gifFigure 8-17 Circuit Breaker Function Disabled