SNVSAQ6D November   2016  – August 2021 LM5170-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)

Each channel of the LM5170-Q1 has a robust 5-A (peak) half bridge driver to drive external N-channel power MOSFETs. As shown in Figure 8-8, the low-side drive is directly powered by VCC, and the high-side driver by the bootstrap capacitor CBT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and CBT is charged by VCC through the boot diode DBT. TI recommends selecting a 0.1-µF or larger ceramic capacitor for CBT, and an ultra-fast diode of 1 A and 100-V ratings for DBT. TI also strongly recommends users to add a 2-Ω to 5-Ω resistor (RBT) in series with DBT to limit the surge charging current and improve the noise immunity of the high-side driver.

GUID-19A82229-3E83-43D2-AD74-6B3E9451A9BD-low.gifFigure 8-8 Bootstrap Circuit for High-Side Bias Supply

During start-up in buck mode, CBT may not be charged initially; the LM5170-Q1 then holds off the high-side driver outputs (HO1 and HO2) and sends LO pulses of 200-ns width in consecutive cycles to pre-charge CBT. When the boot voltage is greater than the 6.5-V boot UV threshold, the high-side drivers output PWM signals at the HO1 and HO2 pins for normal switching action.

During start-up in boost mode, CBT is naturally charged by the normal turnon of the low side MOSFET, therefore there is no such 200-ns pre-charge pulse at the LO pins.

To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive dead time.

To program the dead time, place a resistor RDT across the DT and AGND pins as shown in Figure 8-9.

The dead time tDT as depicted in Figure 8-10 is determined by Equation 15:

Equation 15. GUID-6263DADE-D7EE-4216-B87E-4D69766A86B4-low.gif

Note that this equation is valid for programming tDT between 20 ns and 250 ns. When the power MOSFET is connected to the gate drive, its gate input capacitance CISS becomes a load of the gate drive output, and the HO and LO slew rate are reduced, leading to a reduced effective tDT between the high- and low-side MOSFETs. The user should evaluate the effective tDT to make sure it is adequate to prevent shoot-through between the high- and low-side MOSFETs.

When the DT programmability is not used, simply connect the DT pin to VCC as shown in Figure 8-11, to activate the built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of a driver’s output (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in Figure 8-11 and Figure 8-12. Only when a driver’s output voltage falls below 1.25 V does the other driver starts turnon. The effectiveness of adaptive dead time is greatly reduced if a series gate resistor is used, or if the PCB traces of the gate drive have excessive impedance due to poor layout design.

GUID-BFB78F96-C33B-499F-94AE-0A041969D4E1-low.gifFigure 8-9 Dead Time Programming With DT Pin (Only One Channel is Shown)
GUID-A7D123B7-03BF-41B3-9A60-6AC7BC4C2E7E-low.gifFigure 8-10 Gate Drive Dead Time (Only One Channel is Shown)
GUID-5187C544-4594-4848-870F-505CA6154108-low.gifFigure 8-11 Dead Time Programming With DT Pin (Only One Channel is Shown)
GUID-EE8D8EA0-1B97-486A-9E9D-80A397A1E4BF-low.gifFigure 8-12 Adaptive Dead Time (Only One Channel is Shown)