LMR23610-Q1 SIMPLE SWITCHER® 36 V, 1 A Synchronous Step-Down Converter

7.3.1 Fixed Frequency Peak Current Mode Control

The following operating description of the LMR23610-Q1 will refer to the Functional Block Diagram and to the waveforms in Figure 13. LMR23610-Q1 is a step-down synchronous buck regulator with integrated high-side (HS) and low-side (LS) switches (synchronous rectifier). The LMR23610-Q1 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage swings up to approximately V_IN, and the inductor current i_L increase with linear slope (V_IN – V_OUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of –V_OUT / L. The control parameter of a buck converter is defined as Duty Cycle D = t_ON / T_SW, where t_ON is the high-side switch ON time and T_SW is the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = V_OUT / V_IN.

Figure 13. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)

The LMR23610-Q1 employs fixed frequency peak current mode control. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the peak current threshold to control the ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load condition, the LMR23610-Q1 will operate in PFM mode to maintain high efficiency.

7.3.2 Adjustable Output Voltage

A precision 1.0 V reference voltage is used to maintain a tightly regulated output voltage over the entire operating temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the low-side resistor R_FBB for the desired divider current and use Equation 1 to calculate high-side R_FBT. R_FBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower R_FBT value can be used if static loading is desired to reduce V_OUT offset in PFM operation. Lower R_FBT will reduce efficiency at very light load. Less static current goes through a larger R_FBT and might be more desirable when light load efficiency is critical. But R_FBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger R_FBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the output voltage regulation.

Figure 14. Output Voltage Setting

Equation 1.

7.3.3 Enable/Sync

The voltage on the EN pin controls the ON or OFF operation of LMR23610-Q1. A voltage less than 1 V (typ) will shut-down the device while a voltage higher than 1.6 V (typ) is required to start the regulator. The EN pin is an input and can not be left open or floating. The simplest way to enable the operation of the LMR23610-Q1 is to connect the EN to V_IN. This allows self-start-up of the LMR23610-Q1 when V_IN is within the operation range.

Many applications will benefit from the employment of an enable divider R_ENT and R_ENB (Figure 15) to establish a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. An external logic signal can also be used to drive EN input for system sequencing and protection.

Figure 15. System UVLO by Enable Divider

The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at the EN pin must exceed the SYNC amplitude threshold of 2.8 V (typ) to trip the internal synchronization pulse detector, and the minimum SYNC clock ON and OFF time must be longer than 100ns (typ). A 3.3 V or a higher amplitude pulse signal coupled through a 1 nF capacitor C_SYNC is a good starting point. Keeping R_ENT // R_ENB (R_ENT parallel with R_ENB) in the 100 kΩ range is a good choice. R_ENT is required for this synchronization circuit, but R_ENB can be left unmounted if system UVLO is not needed. LMR23610-Q1 switching action can be synchronized to an external clock from 200 kHz to 2.2 MHz. Figure 17 and Figure 18 show the device synchronized to an external system clock.

Figure 16. Synchronize to external clock

Figure 17. Synchronizing in PWM Mode

Figure 18. Synchronizing in PFM Mode

7.3.4 VCC, UVLO

The LMR23610-Q1 integrates an internal LDO to generate V_CC for control circuitry and MOSFET drivers. The nominal voltage for V_CC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. A high quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage should be placed as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be loaded, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23610-Q1.

VCC under voltage lockout (UVLO) prevents the LMR23610-Q1 from operating until the V_CC voltage exceeds 3.2 V (typ). The VCC UVLO threshold has 400 mV (typ) of hysteresis to prevent undesired shutdown due to temporary V_IN drops.

7.3.5 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Drop-out Conditions

Minimum ON-time, T_{ON_MIN}, is the smallest duration of time that the HS switch can be on. T_{ON_MIN} is typically 60 ns in the LMR23610-Q1. Minimum OFF-time, T_{OFF_MIN}, is the smallest duration that the HS switch can be off. T_{OFF_MIN} is typically 100 ns in the LMR23610-Q1. In CCM operation, T_{ON_MIN} and T_{OFF_MIN}  limit the voltage conversion range given a selected switching frequency.

The minimum duty cycle allowed is:

And the maximum duty cycle allowed is:

Given fixed T_{ON_MIN} and T_{OFF_MIN}, the higher the switching frequency the narrower the range of the allowed duty cycle. In the LMR23610-Q1, a frequency foldback scheme is employed to extend the maximum duty cycle when T_{OFF_MIN} is reached. The switching frequency will decrease once longer duty cycle is needed under low V_IN conditions. Wide range of frequency foldback allows the LMR23610-Q1 output voltage stay in regulation with a much lower supply voltage V_IN. This leads to a lower effective drop-out voltage.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operation supply voltage can be found by:

Equation 4.

At lower supply voltage, the switching frequency will decrease once T_{OFF_MIN} is tripped. The minimum V_IN without frequency foldback can be approximated by:

Equation 5.

Taking considerations of power losses in the system with heavy load operation, V_{IN_MAX} is higher than the result calculated in Equation 4. With frequency foldback, V_{IN_MIN} is lowered by decreased f_SW.

Figure 19. Frequency Foldback at Dropout (V_OUT = 5 V, f_SW = 400 kHz)

7.3.6 Internal Compensation and C_FF

The LMR23610-Q1 is internally compensated as shown in Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. An external feed-forward capacitor C_FF is recommended to be placed in parallel with the top resistor divider R_FBT for optimum transient performance.

Figure 20. Feedforward Capacitor for Loop Compensation

The feed-forward capacitor C_FF in parallel with R_FBT places an additional zero before the cross over frequency of the control loop to boost phase margin. The zero frequency can be found by

Equation 6.

An additional pole is also introduced with C_FF at the frequency of

Equation 7.

The zero f_{Z_CFF} adds phase boost at the crossover frequency and improves transient response. The pole f_P-CFF helps maintaining proper gain margin at frequency beyond the crossover. Table 1 lists the combination of C_OUT, C_FF and R_FBT for typical applications,  designs with similar C_OUT but R_FBT other than recommended value, please adjust C_FF such that (C_FF × R_FBT) is unchanged and adjust R_FBB such that (R_FBT / R_FBB) is unchanged.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most C_FF. Electrolytic capacitors have much larger ESR and the ESR zero frequency

Equation 8.

would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not need any C_FF.

The C_FF creates a time constant with R_FBT that couples in the attenuate output voltage ripple to the FB node. If the C_FF value is too large, it can couple too much ripple to the FB and affect V_OUT regulation. Therefore, C_FF should be calculated based on output capacitors used in the system. At cold temperatures, the value of C_FF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of C_FF can be reduced.

7.3.7 Bootstrap Voltage (BOOT)

The LMR23610-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16V or higher is recommended for stable performance over temperature and voltage.

7.3.8 Over Current and Short Circuit Protection

The LMR23610-Q1 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating.

High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer to Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold I_{HS_LIMIT} which is constant. So the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.

The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is above the LS current limit I_{LS_LIMIT}. The LS switch will be kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit I_{LS_LIMIT}. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. This is somewhat different than the more typical peak current limit, and results in Equation 9 for the maximum load current.

Equation 9.

If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup current protection mode will be activated. In hiccup mode, the regulator will be shut down and kept off for 5 ms typically before the LMR23610-Q1 tries to start again. If over-current or short-circuit fault condition still exist, hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current conditions, prevents over-heating and potential damage to the device.

7.3.9 Thermal Shutdown

The LMR23610-Q1 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170 °C (typ). The device is turned off when thermal shutdown activates. Once the die temperature falls below 155 °C (typ), the device reinitiates the power up sequence controlled by the internal soft-start circuitry.

7.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LMR23610-Q1. When V_EN is below 1 V (typ), the device is in shutdown mode. The LMR23610-Q1 also employs VIN and VCC under voltage lock out protection. If V_IN or V_CC voltage is below their respective UVLO level, the regulator will be turned off.

7.4.2 Active Mode

The LMR23610-Q1 is in Active Mode when V_EN is above the precision enable threshold, V_IN and V_CC are above their respective UVLO level. The simplest way to enable the LMR23610-Q1 is to connect the EN pin to VIN pin. This allows self startup when the input voltage is in the operating range: 4 V to 36 V. Please refer to VCC, UVLO and Enable/Sync for details on setting these operating levels.

In Active Mode, depending on the load current, the LMR23610-Q1 will be in one of three modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple.
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation.
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load.

7.4.3 CCM Mode

CCM operation is employed in the LMR23610-Q1 when the load current is higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple will be at a minimum in this mode and the maximum output current of 1 A can be supplied by the LMR23610-Q1.

7.4.4 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR23610-Q1 will operate in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM, the LS switch is turned off when the inductor current drops to I_{L_ZC} (-40 mA typ). Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation at light load.

At even lighter current loads, Pulse Frequency Modulation (PFM) is activated to maintain high efficiency operation. When either the minimum HS switch ON time (t_{ON_MIN} ) or the minimum peak inductor current I_{PEAK_MIN} (300 mA typ) is reached, the switching frequency will decrease to maintain regulation. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. The external clock synchronizing will not be valid when LMR23610-Q1 enters into PFM mode.

Table 1. L, C_OUT and C_FF Typical Values

8.2.1 Design Requirements

Detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 2 as the input parameters.

8.2.2 Detailed Design Procedure

8.2.2.2 Output Voltage Set-Point

The output voltage of LMR23610-Q1 is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor R_FBT and bottom feedback resistor R_FBB. Equation 10 is used to determine the output voltage:

Equation 10.

Choose the value of R_FBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the V_REF = 1.0 V, the R_FBB value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.

8.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current and the rated current. The inductance is based on the desired peak-to-peak ripple current Δi_L. Since the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use Equation 12 to calculate the minimum value of the output inductor. K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of K_IND should be 30% to 50%. During an instantaneous short or over current operation event, the RMS and peak inductor current can be high. The inductor current rating should be higher than the current limit of the device.

Equation 11.

Equation 12.

In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the comparator signal to noise ratio.

For this design example, choose K_IND = 0.5, the minimum inductor value is calculated to be 20.5 µH. Choose the nearest standard 22 μH ferrite inductor with a capability of 2 A RMS current and 2.5 A saturation current.

8.2.2.5 Output Capacitor Selection

The output capacitor(s), C_OUT, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 13.

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 14.

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The regulator’s control loop usually needs six or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for six clock cycles to maintain the output voltage within the specified range. Equation 15 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 15.

Equation 16.

where

• K_IND = Ripple ratio of the inductor ripple current (Δi_L / I_OUT)
• I_OL = Low level output current during load transient
• I_OH = High level output current during load transient
• V_US = Target output voltage undershoot
• V_OS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR} = ΔV_{OUT_C} = 50 mV, and chose K_IND = 0.5. Equation 13 yields ESR no larger than 100 mΩ and Equation 14 yields C_OUT no smaller than 3.1 μF. For the target over/undershoot range of this design, V_US = V_OS = 5% × V_OUT = 250 mV. The C_OUT can be calculated to be no smaller than 54 μF and 8.5 μF by Equation 15 and Equation 16 respectively. Consider of derating, one 82 μF, 16 V ceramic capacitor with 5 mΩ ESR is used.

8.2.2.6 Feed-Forward Capacitor

The LMR23610-Q1 is internally compensated. Depending on the V_OUT and frequency f_SW, if the output capacitor C_OUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor C_FF can be added in parallel with R_FBT. C_FF is chosen such that phase margin is boosted at the crossover frequency without C_FF. A simple estimation for the crossover frequency (f_X) without C_FF is shown in Equation 17, assuming C_OUT has very small ESR, and C_OUT value is after derating.

Equation 17.

The following equation for C_FF was tested:

Equation 18.

For designs with higher ESR, C_FF is not needed when C_OUT has very high ESR and C_FF calculated from Equation 18 should be reduced with medium ESR. Table 1 can be used as a quick starting point.

For the application in this design example, a 75 pF, 50 V, COG capacitor is selected.

8.2.2.10 Under Voltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENT and R_ENB.  The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the V_IN UVLO level.

Equation 19.

The EN rising threshold (V_ENH) for LMR23610-Q1 is set to be 1.55 V (typ). Choose the value of R_ENB to be 287 kΩ to minimize input current from the supply. If the desired V_IN UVLO level is at 6.0 V, then the value of R_ENT can be calculated using the equation below:

Equation 20.

The above equation yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by below equation, where EN hysteresis (V_{EN_HYS}) is 0.4 V (typ).

Equation 21.

8.2.3 Application Curves

VOUT = 5 V

IOUT = 1 A

fSW = 400 kHz

Figure 22. CCM Mode

VIN = 12 V

VOUT = 5 V

IOUT = 1 A

Figure 24. Start Up by V_IN

VIN = 12 V

VOUT = 5 V

IOUT = 0.1 A to 1 A, 100 mA / μs

Figure 26. Load Transient

VOUT = 5 V

IOUT = 1 A to short

Figure 28. Short Protection

VOUT = 5 V

IOUT = 0 mA

fSW = 400 kHz

Figure 23. PFM Mode

VIN = 12 V

VOUT = 5 V

IOUT = 1 A

Figure 25. Start Up by EN

VOUT = 7 V to 36 V, 2 V / μs

VOUT = 5 V

IOUT = 1 A

Figure 27. Line Transient

VOUT = 5 V

IOUT = short to 1 A

Figure 29. Short Recovery