SNVSAY4F august   2018  – august 2023 LM5155-Q1 , LM51551-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Clock Synchronization (UVLO/SYNC Pin)
      6. 9.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 9.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 9.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 9.3.9  Power-Good Indicator (PGOOD Pin)
      10. 9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
      11. 9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 9.3.12 MOSFET Driver (GATE Pin)
      13. 9.3.13 Overvoltage Protection (OVP)
      14. 9.3.14 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

7 Pin Configuration and Functions

GUID-64FC6397-349F-46BB-9375-2F1B762CD066-low.gif Figure 7-1 12-Pin WSON With Wettable FlanksDSS Package(Top View)
Table 7-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 BIAS P Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
2 VCC P Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a ceramic bypass capacitor from this pin to PGND.
3 GATE O N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET through a short, low inductance path.
4 PGND G Power ground pin. Connect directly to the ground connection of the sense resistor through a low inductance wide and short path.
5 CS I Current sense input pin. Connect to the positive side of the current sense resistor through a short path.
6 COMP O Output of the internal transconductance error amplifier. Connect the loop compensation components between this pin and PGND.
7 AGND G Analog ground pin. Connect to the analog ground plane through a wide and short path.
8 FB I Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output voltage in boost/SEPIC topologies. Connect the low-side feedback resistor to AGND.
9 SS I Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. Connect the ground connection of the capacitor to AGND.
10 RT I Switching frequency setting pin. The switching frequency is programmed by a single resistor between RT and AGND.
11 PGOOD O Power-good indicator. An open-drain output which goes low if FB is below the under voltage threshold. Connect a pullup resistor to the system voltage rail.
12 UVLO/EN/SYNC I Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock can be synchronized to an external clock by applying a negative pulse signal into the UVLO/EN/SYNC pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-side UVLO resistor to AGND.
— EP — Exposed pad of the package. The exposed pad must be connected to AGND and the large ground copper plane to decrease thermal resistance.
(1) G = Ground, I = Input, O = Output, P = Power