SNVSAY4F august   2018  – august 2023 LM5155-Q1 , LM51551-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Clock Synchronization (UVLO/SYNC Pin)
      6. 9.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 9.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 9.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 9.3.9  Power-Good Indicator (PGOOD Pin)
      10. 9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
      11. 9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 9.3.12 MOSFET Driver (GATE Pin)
      13. 9.3.13 Overvoltage Protection (OVP)
      14. 9.3.14 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

9.3.6 Current Sense and Slope Compensation (CS Pin)

The device has a low-side current sense and provides both fixed and optional programmable slope compensation ramps, which help to prevent subharmonic oscillation at high duty cycle. Both fixed and programmable slope compensation ramps are added to the sensed inductor current input for the PWM operation, but only the programmable slope compensation ramp is added to the sensed inductor current input (see Figure 9-17). For an accurate peak current limit operation over the input supply voltage, TI recommends using only the fixed slope compensation (see Figure 8-5).

The device can generate the programmable slope compensation ramp using an external slope resistor (RSL) and a sawtooth current source with a slope of 30 μA × fRT. This current flows out of the CS pin.

GUID-B29BB6CF-690E-458F-948E-2D6E541F778E-low.gifFigure 9-17 Current Sensing and Slope Compensation
GUID-C7EEF984-72F5-40D9-8B04-5B4496002E70-low.gifFigure 9-18 Slope Compensation Ramp (a) at PWM Comparator Input
GUID-85030889-5414-4EA6-B1B5-1BEB51A44344-low.gifFigure 9-19 Slope Compensation Ramp (b) at Current Limit Comparator Input

Use Equation 6 to calculate the value of the peak slope current (ISLOPE) and use Equation 7 to calculate the value of the peak slope voltage (VSLOPE).

Equation 6. GUID-DFEDAEA5-1B76-4EAB-A45B-B7EC28681AAF-low.gif
Equation 7. GUID-2118EE0D-F38A-44C1-B57D-16F0441B151D-low.gif

where

  • fSYNC = fRT if clock synchronization is not used.

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation in boost topology should satisfy the following inequality:

Equation 8. GUID-41E2F4A7-1971-4A7D-97E7-A87B5E3CEDD6-low.gif

where

  • VF is a forward voltage drop of D1, the external diode.

The recommended value for margin to cover non-ideal factors is 1.2. If required, RSL can be added to further increase the slope of the compensation ramp. Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope compensation. The RSL value to achieve 82% of the sensed inductor current falling slope is calculated as shown in Equation 9.

Equation 9. GUID-3185B107-9C8D-4D93-9450-2AC408C556B0-low.gif

If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used, the fSW frequency equals the fSYNC frequency. The maximum value for the RSL resistance is 2 kΩ.