SNVSAY4F august   2018  – august 2023 LM5155-Q1 , LM51551-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Clock Synchronization (UVLO/SYNC Pin)
      6. 9.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 9.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 9.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 9.3.9  Power-Good Indicator (PGOOD Pin)
      10. 9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
      11. 9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 9.3.12 MOSFET Driver (GATE Pin)
      13. 9.3.13 Overvoltage Protection (OVP)
      14. 9.3.14 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

9.3.1 Line Undervoltage Lockout (UVLO/SYNC Pin)

The device has a dual-level UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V, the UVLO pin voltage is in between the enable threshold (VEN), and the UVLO threshold (VUVLO) for more than 1.5 µs (see Section 9.3.5 for more details), the device starts up and an internal configuration starts. The device typically requires a 65-µs internal start-up delay before entering standby mode. In standby mode, the VCC regulator and RT regulator are operational, SS pin is grounded, and there is no switching at the GATE output.

GUID-FE4211EE-B1E3-4E03-A86F-1783362B8DCA-low.gifFigure 9-1 Line UVLO and Enable

When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a soft-start sequence starts if the VCC voltage is greater than 4.5 V, or 50 µs after the VCC voltage exceeds the 2.85-V VCC UV threshold (VVCC-UVLO), whichever comes first. UVLO hysteresis is accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched on or off. When the UVLO pin voltage exceeds the UVLO threshold, the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin voltage is less than the enable threshold (VEN), the device enters shutdown mode after a 35-µs (typical) delay with all functions disabled.

GUID-B8329223-C0FF-48B1-A52B-46A1DFFD7216-low.gifFigure 9-2 Boost Start-Up Waveforms Case 1: Start-Up by 2.85-V VCC UVLO, UVLO Toggle After Start-Up
GUID-DE88A793-A5E8-44DA-92F3-3C18A3BE51E0-low.gifFigure 9-3 Boost Start-Up Waveforms Case 2: Start-Up When VCC > 4.5 V, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V (typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be calculated as shown in Equation 1 and Equation 2.

Equation 1. GUID-1A8B133E-F74B-418D-8732-4698E14DDBA4-low.gif

where

  • VSUPPLY(ON) is the desired start-up voltage of the converter.
  • VSUPPLY(OFF) is the desired turnoff voltage of the converter.
Equation 2. GUID-8BA5B2F1-FAA0-4409-A281-B8F54962801A-low.gif

A UVLO capacitor (CUVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-μA hysteresis current turns on.

GUID-FCC4D8B6-4973-41B8-968E-A9908CED5BDF-low.gifFigure 9-4 Line UVLO using Three UVLO Resistors

Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.