SNVSB38D September   2019  – January 2021 UCC12050

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications and Uses
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 UVLO, Power-Up, and Power-Down Behavior
      3. 7.3.3 VISO Load Recommended Operating Area
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 External Clocking and Synchronization
      6. 7.3.6 VISO Output Voltage Selection
      7. 7.3.7 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VISO Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical and Packaging Information

6.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
GENERAL
CLR External clearance(1)Shortest terminal-to-terminal distance through air> 8mm
CPGExternal creepage(1)Shortest terminal-to-terminal distance across the package surface> 8mm
DTIDistance through the insulationMinimum internal gap (internal clearance)> 120µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112> 600V
Material groupAccording to IEC 60664-1I
Overvoltage CategoryRated mains voltage ≤ 300 VRMSI-IV
Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE V 0884-11:2017-01(2) 
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)1697VPK
VIOWMMaximum working isolation voltageAC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test1200VRMS
DC voltage1697VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)		7071VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)		6250VPK
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1696 VPK, tm = 10 s		≤ 5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2262 VPK, tm = 10 s		≤ 5
Method b1: At routine test (100% production) and preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s		≤ 5
CIOBarrier capacitance, input to output(5)VIO = 0.4 sin (2πft), f = 1 MHz~3.5pF
RIOIsolation resistance, input to output(5)VIO = 500 V, TA = 25°C> 1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V at TS = 150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5000 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production)5000VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device