The LM5163-Q1 synchronous buck converter is designed to regulate over a wide input voltage range, minimizing the need for external surge suppression components. A minimum controllable on-time of 50ns facilitates large step-down conversion ratios, enabling the direct step-down from a 48V nominal input to low-voltage rails for reduced system complexity and solution cost. The LM5163-Q1 operates during input voltage dips as low as 6V, at nearly 100% duty cycle if needed, making the device an excellent choice for high-performance 48V battery automotive applications and MHEV/EV systems.
With integrated high-side and low-side power MOSFETs, the LM5163-Q1 delivers up to 0.5A of output current. A constant on-time (COT) control architecture provides nearly constant switching frequency with excellent load and line transient response. Additional features of the LM5163-Q1 include ultra-low IQ and diode emulation mode operation for high light-load efficiency, innovative peak and valley overcurrent protection, integrated VCC bias supply and bootstrap diode, precision enable and input UVLO, and thermal shutdown protection with automatic recovery. An open-drain PGOOD indicator provides sequencing, fault reporting, and output voltage monitoring.
The LM5163-Q1 is qualified to automotive AEC-Q100 grade 1 and is available in a 8-pin SO PowerPAD™ package. The device 1.27mm pin pitch provides adequate spacing for high-voltage applications.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | GND | G | Ground connection for internal circuits |
2 | VIN | P/I | Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect directly to the input supply of the buck converter with short, low impedance paths. |
3 | EN/UVLO | I | Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence begins. |
4 | RON | I | On-time programming pin. A resistor between this pin and GND sets the buck switch on-time. |
5 | FB | I | Feedback input of voltage regulation comparator |
6 | PGOOD | O | Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an external pullup resistor between 10 kΩ to 100 kΩ. |
7 | BST | P/I | Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF 50-V X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
8 | SW | P | Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor. |
— | EP | — | Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN to GND | –0.3 | 100 | V |
EN to GND | –0.3 | 100 | ||
FB to GND | –0.3 | 5.5 | ||
RON to GND | –0.3 | 5.5 | ||
Bootstrap capacitor | External BST to SW capacitance | 1.5 | 2.5 | nF |
Output voltage | BST to GND | –0.3 | 105.5 | V |
BST to SW | –0.3 | 5.5 | ||
SW to GND | –1.5 | 100 | ||
SW to GND (20-ns transient) | –3 | |||
PGOOD to GND | –0.3 | 14 | ||
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC-Q100-002 HBM ESD Classification Level 2, all pins(1) | ±2000 | V |
Charged device model (CDM), per AEC-Q100-011 CDM ESD Classification level C4B. All pins except 1, 4, 5, and 8 | ±500 | |||
Charged device model (CDM), per AEC-Q100-011 CDM ESD Classification level C4B. Pins 1, 4, 5, and 8 | ±750 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage | 6 | 100 | V | |
VSW | Switch node voltage | 100 | V | ||
VEN/UVLO | Enable voltage | 100 | V | ||
ILOAD | Load current | 0.5 | 0.6 | A | |
FSW | Switching frequency | 1000 | kHz | ||
CBST | External BST to SW capacitance | 2.2 | nF | ||
tON | Programmable on-time | 50 | 10000 | ns |
THERMAL METRIC(1) | LM5163-Q1 | UNIT | |
---|---|---|---|
DDA (SOIC) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 43.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 59.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.1 | °C/W |
ΨJT | Junction-to-top characterization parameter | 4.0 | °C/W |
ΨJB | Junction-to-board characterization parameter | 16.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
IQ-SHUTDOWN | VIN shutdown current | VEN = 0 V | 3 | 15 | µA | |
IQ-SLEEP1 | VIN sleep current | VEN = 2.5 V, VFB = 1.5 V | 10.5 | 25 | µA | |
IQ-ACTIVE | VIN active current | VEN = 2.5 V | 600 | 880 | µA | |
EN/UVLO | ||||||
VSD-RISING | Shutdown threshold | VEN/UVLO rising | 1.1 | V | ||
VSD-FALLING | Shutdown threshold | VEN/UVLO falling | 0.45 | V | ||
VEN-RISING | Enable threshold | VEN/UVLO rising | 1.45 | 1.5 | 1.55 | V |
VEN-FALLING | Enable threshold | VEN/UVLO falling | 1.35 | 1.4 | 1.44 | V |
FEEDBACK | ||||||
VREF | FB regulation voltage | VFB falling | 1.181 | 1.2 | 1.218 | V |
TIMING | ||||||
tON1 | On-time1 | VVIN = 6 V, RRON = 75 kΩ | 5000 | ns | ||
tON2 | On-time2 | VVIN = 6 V, RRON = 25 kΩ | 1650 | ns | ||
tON3 | On-time3 | VVIN = 12 V, RRON = 75 kΩ | 2550 | ns | ||
tON4 | On-time4 | VVIN = 12 V, RRON = 25 kΩ | 830 | ns | ||
PGOOD | ||||||
VPG-UTH | FB upper threshold for PGOOD high to low | VFB rising | 1.105 | 1.14 | 1.175 | V |
VPG-LTH | FB lower threshold for PGOOD high to low | VFB falling | 1.055 | 1.08 | 1.1 | V |
VPG-HYS | PGOOD upper and lower threshold hysteresis | VFB falling | 60 | mV | ||
RPG | PGOOD pulldown resistance | VFB = 1 V | 30 | Ω | ||
BOOTSTRAP | ||||||
VBST-UV | Gate drive UVLO | VBST rising | 2.7 | 3.4 | V | |
POWER SWITCHES | ||||||
RDSON-HS | High-side MOSFET RDSON | ISW = –100 mA | 0.725 | Ω | ||
RDSON-LS | Low-side MOSFET RDSON | ISW = 100 mA | 0.33 | Ω | ||
SOFT START | ||||||
tSS | Internal soft-start time | 1.75 | 3 | 4.75 | ms | |
CURRENT LIMIT | ||||||
IPEAK1 | Peak current limit threshold (HS) | 0.63 | 0.75 | 0.87 | A | |
IPEAK2 | Peak current limit threshold (LS) | 0.63 | 0.75 | 0.87 | A | |
IDELTA-ILIM | Min of (IPEAK1 or IPEAK2) minus IVALLEY | 100 | mA | |||
IVALLEY | Valley current limit threshold | 0.5 | 0.6 | 0.72 | A | |
THERMAL SHUTDOWN | ||||||
TSD | Thermal shutdown threshold | TJ rising | 175 | °C | ||
TSD-HYS | Thermal shutdown hysteresis | 10 | °C |
At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified. At TA = 25°C, VOUT = 12 V, LO = 68 µH, RRON = 105 kΩ, unless otherwise specified.
The LM5163-Q1 is an easy-to-use, ultra-low IQ constant on-time (COT) synchronous step-down buck regulator. With integrated high-side and low-side power MOSFETs, the LM5163-Q1 is a low-cost, highly efficient buck converter that operates from a wide input voltage of 6 V to 100 V, delivering up to 0.5-A DC load current. The LM5163-Q1 is available in an 8-pin SO PowerPAD package with 1.27-mm pin pitch for adequate spacing in high-voltage applications. This constant on-time (COT) converter is ideal for low-noise, high-current, and fast load transient requirements, operating with a predictive on-time switching pulse. Over the input voltage range, input voltage feedforward is employed to achieve a quasi-fixed switching frequency. A controllable on-time as low as 50 ns permits high step-down ratios and a minimum forced off-time of 50 ns provides extremely high duty cycles, allowing VIN to drop close to VOUT before frequency foldback occurs. At light loads, the device transitions into an ultra-low IQ mode to maintain high efficiency and prevent draining battery cells connected to the input when the system is in standby. The LM5163-Q1 implements a smart peak and valley current limit detection circuit to ensure robust protection during output short circuit conditions. Control loop compensation is not required for this regulator, reducing design time and external component count.
The LM5163-Q1 incorporates additional features for comprehensive system requirements, including an open-drain power good circuit for the following:
These features enable a flexible and easy-to-use platform for a wide range of applications. The LM5163-Q1 supports a wide range of end-equipment systems requiring a regulated output from a high input supply where the transient voltage deviates from the DC level. The following are examples of such end equipment systems:
The pin arrangement is designed for a simple layout requiring only a few external components.
The LM5163-Q1 step-down switching converter employs a constant on-time (COT) control scheme. The COT control scheme sets a fixed on-time tON of the high-side FET using a timing resistor (RON). The tON is adjusted as Vin changes and is inversely proportional to the input voltage to maintain a fixed frequency when in continuous conduction mode (CCM). After expiration of tON, the high-side FET remains off until the feedback pin is equal or below the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple voltage that is in phase with the inductor current during the off-time. Furthermore, this change in feedback voltage during the off-time must be large enough to dominate any noise present at the feedback node. The minimum recommended ripple voltage is 20 mV. See Table 6-1 for different types of ripple injection schemes that ensure stability over the full input voltage range.
During a rapid start-up or a positive load step, the regulator operates with minimum off-times until regulation is achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot. When regulating the output in steady-state operation, the off-time automatically adjusts itself to produce the SW-pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the switching frequency FSW is programmed by the RRON resistor. Use Equation 1 to calculate the switching frequency.
TYPE 1 | TYPE 2 | TYPE 3 |
---|---|---|
Lowest Cost | Reduced Ripple | Minimum Ripple |
Equation 2. Equation 3. | Equation 4. Equation 5. Equation 6. | Equation 7. Equation 8. Equation 9. |
Table 6-1 presents three different methods for generating appropriate voltage ripple at the feedback node. Type-1 ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated voltage ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and through series resistance RESR. The capacitive ripple component is out of phase with the inductor current and does not decrease monotonically during the off-time. The resistive ripple component is in phase with the inductor current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off-time. Equation 2 and Equation 3 define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback node.
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple are reduced by a factor of VOUT / VFB1.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details on this topic.
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current reduces switching loss, and preventing negative current conduction reduces conduction loss. Power conversion efficiency is higher in a DEM converter than an equivalent forced-PWM CCM converter. With DEM operation, the duration that both power MOSFETs remain off progressively increases as load current decreases. When this idle duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA quiescent current from the input.
The LM5163-Q1 contains an internal linear regulator that is powered from VIN with a nominal output of 5 V, eliminating the need for an external capacitor to stabilize the linear regulator. The internal VCC regulator supplies current to internal circuit blocks including the synchronous FET driver and logic circuits. The input pin (VIN) can be connected directly to line voltages up to 100 V. As the power MOSFET has a low total gate charge, use a low bootstrap capacitor value to reduce the stress on the internal regulator. It is required to select a high-quality 2.2-nF 50-V X7R ceramic bootstrap capacitor as specified in the Absolute Maximum Ratings section. Selecting a higher value capacitance stresses the internal VCC regulator and damages the device. A lower capacitance than required is not sufficient to drive the internal gate of the power MOSFET. An internal diode connects from the VCC regulator to the BST pin to replenish the charge in the high-side gate drive bootstrap capacitor when the SW voltage is low.
The feedback voltage at FB is compared to an internal 1.2-V reference. The LM5163-Q1 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage, VREF. A resistor divider programs the ratio from output voltage VOUT to FB.
For a target VOUT setpoint, use Equation 10 to calculate RFB2 based on the selected RFB1.
TI recommends selecting RFB1 in the range of 100 kΩ to 1 MΩ for most applications. A larger RFB1 consumes less DC current, which is mandatory if light-load efficiency is critical. RFB1 larger than 1 MΩ is not recommended as the feedback path becomes more susceptible to noise. It is important to route the feedback trace away from the noisy area of the PCB and keep the feedback resistors close to the FB pin.
The LM5163-Q1 employs an internal soft-start control ramp that allows the output voltage to gradually reach a steady-state operating point, thereby reducing start-up stresses and current surges. The soft-start feature produces a controlled, monotonic output voltage start-up. The soft-start time is internally set to 3 ms.
The on-time of the LM5163-Q1 high-side FET is determined by the RRON resistor and is inversely proportional to the input voltage, VIN. The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. Use Equation 11 to calculate the on-time.
Use Equation 12 to determine the RRON resistor to set a specific switching frequency in CCM.
Select RRON for a minimum on-time (at maximum VIN) greater than 50 ns for proper operation. In addition to this minimum on-time, the maximum frequency for this device is limited to 1 MHz.
The LM5163-Q1 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor current. The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold (0.75 A). To protect the converter from potential current runaway conditions, the LM5163-Q1 includes a foldback valley current limit feature, set at 0.6 A, that is enabled if a peak current limit is detected. As shown in Figure 6-1, if the peak current in the high-side MOSFET exceeds 0.75 A (typical), the present cycle is immediately terminated regardless of the programmed on-time (tON), the high-side MOSFET is turned off and the foldback valley current limit is activated. The low-side MOSFET remains on until the inductor current drops below this foldback valley current limit, after which the next on-pulse is initiated. This method folds back the switching frequency to prevent overheating and limits the average output current to less than 0.75 A to ensure proper short-circuit and heavy-load protection of the LM5163-Q1.
Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.75 A enables the foldback valley current limit set at 0.6 A. This innovative current limit scheme enables ultra-low duty-cycle operation, permitting large step-down voltage conversions while ensuring robust protection of the converter.
The LM5163-Q1 integrates an N-channel buck switch and associated floating high-side gate driver. The gate-driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap diode. A high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the voltage to the high-side driver during the buck switch on-time. See the Section 6.3.2 section for limitations. During the off-time, the SW pin is pulled down to approximately 0 V, and the bootstrap capacitor charges from the internal VCC through the internal bootstrap diode. The minimum off-timer, set to 50 ns (typical), ensures a minimum time each cycle to recharge the bootstrap capacitor. When the on-time is less than 300 ns, the minimum off-timer is forced to 250 ns to ensure that the BST capacitor is charged in a single cycle. This is vital during wake up from sleep mode when the BST capacitor is most likely discharged.
The LM5163-Q1 provides an internal low-side synchronous rectifier N-channel MOSFET. This MOSFET provides a low-resistance path for the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier operates in a diode emulation mode. Diode emulation enables the regulator to operate in a pulse-skipping mode during light load conditions. This mode leads to a reduction in the average switching frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to switching frequency, are significantly reduced at very light loads and efficiency is improved. This pulse-skipping mode also reduces the circulating inductor current and losses associated with conventional CCM at light loads.
The LM5163-Q1 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the converter is in a low-current shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in standby mode. In standby mode, the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the rising threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the minimum operating voltage of the regulator. Use Equation 13 and Equation 14 to calculate the input UVLO turnon and turnoff voltages, respectively.
TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN. If EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are active.
The LM5163-Q1 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level. Use the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference VREF, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 90% of VREF, an internal 25-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.
The LM5163-Q1 includes an internal junction temperature monitor to protect the device in the event of a higher than normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs to prevent further power dissipation and temperature rise. The LM5163-Q1 initiates a restart sequence when the junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C. This is a non-latching protection, so the device cycles into and out of thermal shutdown if the fault persists.
EN/UVLO provides ON and OFF control for the LM5163-Q1. When VEN/UVLO is below approximately 1.1 V, the device is in shutdown mode. Both the internal linear regulator and the switching regulator are off. The quiescent current in shutdown mode drops to 3 µA at VIN = 24 V. The LM5163-Q1 also employs internal bias rail undervoltage protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off.
The LM5163-Q1 is in active mode when VEN/UVLO is above the precision enable threshold and the internal bias rail is above its UV threshold. In COT active mode, the LM5163-Q1 is in one of three modes depending on the load current:
The Section 6.3.1 section gives a brief introduction to the LM5163-Q1 diode emulation (DEM) feature. The converter enters DEM during light-load conditions when the inductor current decays to zero and the synchronous MOSFET is turned off to prevent negative current in the system. In the DEM state, the load current is lower than half of the peak-to-peak inductor current ripple and the switching frequency decreases when the load is further decreased as the device operates in a pulse skipping mode. A switching pulse is set when VFB drops below 1.2 V.
As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the input power supply. The input quiescent current (IQ) required by the LM5163-Q1 decreases to 10 µA in sleep mode, improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned off to ensure very low current consumption by the device. Such low IQ renders the LM5163-Q1 as the best option to extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active to detect when the FB voltage drops below the internal reference VREF and the converter transitions out of sleep mode into active mode. There is a 9-µs wake-up delay from sleep to active states.
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
The LM5163-Q1 requires only a few external components to step down from a wide range of supply voltages to a fixed output voltage. Several features are integrated to meet system design requirements, including the following:
To expedite and streamline the process of designing of a LM5163-Q1-based converter, a comprehensive LM5163-Q1quickstart calculator is available for download to assist the designer with component selection for a given application. This tool is complemented by the availability of an evaluation module (EVM), numerous PSPICE models, as well as TI's WEBENCH® Power Designer. In order to modify the LM5164-Q1EVM-041 for the LM5163-Q1, change the inductor LO to 120 µH, the resistor RA to 226 kΩ, and the capacitance COUT to 22 µF. See Figure 7-1 for the LM5163-Q1 applications circuit.
Figure 7-1 shows the schematic for a 12-V, 0.5-A COT converter.
This and subsequent design examples are provided herein to showcase the LM5163-Q1 converter in several different applications. Depending on the source impedance of the input supply bus, an electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage and high output current operating conditions. See the Section 7.3 section for more details.
The target full-load efficiency is 92% based on a nominal input voltage of 48 V and an output voltage of 12 V. The required input voltage range is 15 V to 100 V. The LM5163-Q1 delivers a fixed 12-V output voltage. The switching frequency is set by resistor RRON at 300 kHz. The output voltage soft-start time is 3 ms. Table 7-1 lists the required components. Refer to the LM5164-Q1EVM-041 User's Guide for more detail.
COUNT | REF DES | VALUE | DESCRIPTION | PART NUMBER | MANUFACTURER |
---|---|---|---|---|---|
2 | CIN | 2.2 µF | Capacitor, Ceramic, 2.2 µF, 100 V, X7R, 10% | CGA6N3X7R2A225K230AB | TDK |
1 | COUT | 22 µF | Capacitor, Ceramic, 22 µF, 25 V, X7R, 10% | TMK325B7226KMHT | Taiyo Yuden |
1 | CA | 3300 pF | Capacitor, Ceramic, 3300 pF, 16 V, X7R, 10% | CGA3E2X7R2A332K080AA | TDK |
1 | CB | 56 pF | Capacitor, Ceramic, 56 pF, 50 V, X7R, 10% | C0603C560J5GACTU | Kemet |
1 | CBST | 2.2 nF | Capacitor, Ceramic, 2200 pF, 50 V, X7R, 10% | GCM155R71H222KA37D | MuRata |
1 | LO | 120 µH | Inductor, 120 µH, 210 mΩ, 1.65 A | MSS1260-124KL | Coilcraft |
1 | RRON | 100 kΩ | Resistor, Chip, 100 k, 1%, 0.1 W, 0603 | RG1608P-1053-B-T5 | Susumu Co Ltd |
1 | RFB1 | 453 kΩ | Resistor, Chip, 453 k, 1%, 0.1 W, 0603 | RT0603BRD07448KL | Yageo |
1 | RFB2 | 49.9 kΩ | Resistor, Chip, 49.9 k, 1%, 0.1 W, 0603 | RG1608P-4992-B-T5 | Susumu Co Ltd |
1 | RA | 226 kΩ | Resistor, Chip, 226 k, 1%, 0.1W, 0603 | RT0603BRD07226KL | Yageo |
1 | U1 | Wide VIN synchronous buck converter | LM5163QDDARQ1 | TI |