SNVSC75A April 2023 – July 2024 LM5171-Q1
ADVANCE INFORMATION
Figure 6-36 shows the format of a single read from a defined register address. First, the Controller issues a start condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that a write operation is conducted. Upon receiving an acknowledge from the Peripheral the Controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the internal I 2 C register number to the defined value. Then the Controller issues a repeat start condition and the seven-bit I 2 C address followed by a one to signify that a read operation has conducted. Upon receiving a third acknowledge, the Controller releases the bus to the device. The device then returns the eight-bit data value from the register on the bus. The Controller does not acknowledge (nACK) and issues a stop condition. This action concludes the register read.