SNVSCC4A October   2023  – September 2024 LP5811

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Synchronous Boost Converter
        1. 6.3.1.1 Undervoltage Lockout
        2. 6.3.1.2 Enable and Soft Start
        3. 6.3.1.3 Switching Frequency
        4. 6.3.1.4 Current Limit Operation
        5. 6.3.1.5 Boost PWM Mode
        6. 6.3.1.6 Boost PFM Mode
      2. 6.3.2 Analog Dimming
      3. 6.3.3 PWM Dimming
      4. 6.3.4 Autonomous Animation Engine Control
        1. 6.3.4.1 Animation Engine Pattern
        2. 6.3.4.2 Sloper
        3. 6.3.4.3 Animation Engine Unit (AEU)
        4. 6.3.4.4 Animation Pause Unit (APU)
      5. 6.3.5 Protections and Diagnostics
        1. 6.3.5.1 Overvoltage Protection
        2. 6.3.5.2 Output Short-to-Ground Protection
        3. 6.3.5.3 LED Open Detections
        4. 6.3.5.4 LED Short Detections
        5. 6.3.5.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Parameters
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Inductor Selection
        2. 7.2.3.2 Output Capacitor Selection
        3. 7.2.3.3 Input Capacitor Selection
        4. 7.2.3.4 Program Procedure
        5. 7.2.3.5 Programming Example
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Timing Requirements

Unless specified otherwise, typical characteristics apply over the full ambient temperature range (–40°C < TA < +85°C ), VIN = 3.6 V, VCC = 5 V, CIN = 1 μF, COUT = 1 μF.
I2C Timing Requirements MIN NOM MAX UNIT
Standard-mode
fSCL SCL clock frequency 0 100 kHz
tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 µs
tLOW LOW period of the SCL clock 4.7 µs
tHIGH HIGH period of the SCL clock 4 µs
tSU_STA Set-up time for a repeated START condition 4.7 µs
tHD_DAT Data hold time 0 µs
tSU_DAT Data set-up time 250 ns
tr Rise time of both SDA and SCL signals 1000 ns
tf Fall time of both SDA and SCL signals 300 ns
tSU_STO Set-up time for STOP condition 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
Cb Capacitive load for each bus line 400 pF
Fast-mode
fSCL SCL clock frequency 0 400 kHz
tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 µs
tLOW LOW period of the SCL clock 1.3 µs
tHIGH HIGH period of the SCL clock 0.6 µs
tSU_STA Set-up time for a repeated START condition 0.6 µs
tHD_DAT Data hold time 0 µs
tSU_DAT Data set-up time 100 ns
tr Rise time of both SDA and SCL signals 300 ns
tf Fall time of both SDA and SCL signals 300 ns
tSU_STO Set-up time for STOP condition 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
Cb Capacitive load for each bus line 400 pF
Fast-mode Plus
fSCL SCL clock frequency 0 1000 kHz
tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.26 µs
tLOW LOW period of the SCL clock 0.5 µs
tHIGH HIGH period of the SCL clock 0.26 µs
tSU_STA Set-up time for a repeated START condition 0.26 µs
tHD_DAT Data hold time 0 µs
tSU_DAT Data set-up time 50 ns
tr Rise time of both SDA and SCL signals 120 ns
tf Fall time of both SDA and SCL signals 120 ns
tSU_STO Set-up time for STOP condition 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
Cb Capacitive load for each bus line 550 pF
Misc. Timing Requirements
fCLK_EX VSYNC input clock frequency 6 MHz