SNVSCE6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

10.3.5.1 Sense Time Delay Configuration

SENSE time delay (tCTS) occurs when the RESET is transitioning from a non-fault state (VOH) to a fault state (VOL). The time delay (tCTS) can be programmed by connecting a capacitor between CTS pin and GND.

The relationship between external capacitor CCTS_EXT (typ) and the time delay tCTS (typ) is given by Equation 4.

Equation 4. tCTS (typ) = RCTS (typ) x CCTS_EXT (typ) + tCTS (no cap) x 10-6

RCTS (typ) = is in mega ohms (MΩ)

CCTS_EXT (typ) = is given in microfarads (μF)

tCTS (typ) = is the sense time delay/delays

The sense delay varies according to three variables: the external capacitor (CCTS_EXT), CTS pin internal resistance (RCTS) provided in Section 7.5, and the constant ( tCTS (no cap)) provided in Section 7.6. The minimum and maximum variance due to the constant is show in Equation 5 and Equation 6:

Equation 5. tCTS (min) = RCTS (min) x CCTS_EXT (min) + tCTS (no cap (min)) x 10-6
Equation 6. tCTR (max) = RCTS (max) x CCTS_EXT (max) + tCTSx (no cap (max)) x 10-6

The recommended maximum sense delay capacitor for the TPS3762-Q1 is 10μF as this makes sure there is enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) and system noise can cause the internal circuit to trip unpredictably. This leads to a variation in time delay where the delay accuracy can be worse in the presence of system noise.

* Leakages on the capacitor can effect accuracy of sense time delay.