SNVSCE6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

10.3.2.2 SENSE Hysteresis

TPS3762-Q1 device offers built-in hysteresis around the UV and OV thresholds to avoid erroneous RESET deassertions. The hysteresis is opposite to the threshold voltage; for overvoltage options the hysteresis is subtracted from the positive threshold (VITP), for undervoltage options hysteresis is added to the negative threshold (VITN).

TPS3762-Q1 Hysteresis (Undervoltage & Overvoltage Active-Low)Figure 10-5 Hysteresis (Undervoltage & Overvoltage Active-Low)
Table 10-1 Common Adjustable Hysteresis Lookup Table
TARGETDEVICE HYSTERESIS OPTION
ADJUSTABLE THRESHOLDTOPOLOGYRELEASE VOLTAGE (V)
800mVOvervoltage

784mV

-2%

800mVOvervoltage

760mV

-5%
800mVOvervoltage

720mV

-10%
800mVUndervoltage

816mV

2%

800mVUndervoltage

840mV

5%
800mVUndervoltage

880mV

10%

Table 10-1 shows a sample of hysteresis for the 800mV adjustable variant of TPS3762-Q1.

Knowing the amount of hysteresis voltage, the release voltage for the undervoltage (UV) channel is (VITN + VHYS) and for the overvoltage (OV) channel is (VITP - VHYS).

Undervoltage (UV)

VITN = 800mV

Voltage Hysteresis (VHYS) = 2% = 16mV

Hysteresis Accuracy = +1.5% to +2.5% = 16.24mV to 16.4mV

Release Voltage = VITN + VHYS = 816.24mV to 816.4mV

Overvoltage (OV)

VITP = 800mV

Voltage Hysteresis (VHYS) = 2% = 16mV

Hysteresis Accuracy = +1.5% to +2.5% = 16.24mV to 16.4mV

Release Voltage = VITP - VHYS = 783.6mV to 783.76mV