SNVSCG7 November   2024 LM5190

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN)
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC, BIAS)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PGOOD)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Low Dropout Mode
      7. 6.3.7  Dual Random Spread Spectrum (DRSS)
      8. 6.3.8  Soft Start
      9. 6.3.9  Output Voltage Setpoint (FB)
      10. 6.3.10 Minimum Controllable On Time
      11. 6.3.11 Inductor Current Sense (ISNS+, VOUT)
      12. 6.3.12 Voltage Loop Error Amplifier
      13. 6.3.13 Current Monitor, Programmable Current Limit, and Current Loop Error Amplifier (IMON/ILIM, ISET)
      14. 6.3.14 Dual Loop Architecture
      15. 6.3.15 PWM Comparator
      16. 6.3.16 Slope Compensation
      17. 6.3.17 Hiccup Mode Current Limiting
      18. 6.3.18 High-Side and Low-Side Gate Drivers (HO, LO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM Mode and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 High Efficiency 400kHz CC-CV Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Buck Inductor
          2. 7.2.1.2.2 Current-Sense Resistance
          3. 7.2.1.2.3 Output Capacitors
          4. 7.2.1.2.4 Input Capacitors
          5. 7.2.1.2.5 Frequency Set Resistor
          6. 7.2.1.2.6 Feedback Resistors
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate-Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.1.2 Output Capacitors

The output capacitor combined with the control loop response make sure the output voltage stays within the dynamic transient tolerance specifications. The usual boundaries restricting the output capacitor are driven by finite available PCB area, component size, and cost. The equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor dominates shaping the load transient response as the load step amplitude and slew rate increase.

The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for load transient events. Typically, ceramic capacitors provide low ESR to reduce the output voltage ripple and noise spikes, while tantalum or electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events.

Figure 7-1 conceptually illustrates the relevant current waveforms during both load step-down and step-up transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as fast as possible during and after the load step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.

LM5190 Load Transient Response Representation Showing COUT Charge Surplus or Deficit Figure 7-1 Load Transient Response Representation Showing COUT Charge Surplus or Deficit

For example, in a typical regulator application of 12V input to 3.3V output voltage, the load-off transient represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –VLOAD / LOUT. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below the nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔVOVERSHOOT with step reduction in output current given by ΔILOAD), the output capacitance must be larger than:

Equation 15. C O U T ≥ L O U T × ∆ I L O A D 2 V L O A D + ∆ V O V E R S H O O T 2 - V L O A D 2

Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVLOAD, choose an output capacitance that is larger than that given by Equation 16.

Equation 16. C O U T ≥ ∆ I L O U T 8 × f S W × ∆ V L O A D 2 - R E S R × ∆ I L O U T 2

The ESR of a capacitor is provided in the manufacturer data sheet, either explicitly as a specification or implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic capacitors have significant ESR, 5mΩ and above, and relatively large ESL, 5nH to 20nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors have low-ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature.

Ignoring the ESR term in Equation 16 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. Use Equation 15 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification.

A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with the low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with the large bulk capacitance provides low-frequency energy storage to cope with load transient demands.