SNVSCL9A March   2011  – October 2024 LM3481-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings: LM3481-Q1
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Overvoltage Protection
      2. 6.3.2 Bias Voltage
      3. 6.3.3 Slope Compensation Ramp
      4. 6.3.4 Frequency Adjust, Synchronization, and Shutdown
      5. 6.3.5 Undervoltage Lockout (UVLO) Pin
      6. 6.3.6 Short-Circuit Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Boost Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design with WEBENCH Tools
          2. 7.2.1.2.2  Power Inductor Selection
          3. 7.2.1.2.3  Programming the Output Voltage and Output Current
          4. 7.2.1.2.4  Current Limit With Additional Slope Compensation
          5. 7.2.1.2.5  Power Diode Selection
          6. 7.2.1.2.6  Power MOSFET Selection
          7. 7.2.1.2.7  Input Capacitor Selection
          8. 7.2.1.2.8  Output Capacitor Selection
          9. 7.2.1.2.9  Driver Supply Capacitor Selection
          10. 7.2.1.2.10 Compensation
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Typical SEPIC Converter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Power MOSFET Selection
          2. 7.2.2.2.2 Power Diode Selection
          3. 7.2.2.2.3 Selection of Inductors L1 and L2
          4. 7.2.2.2.4 Sense Resistor Selection
          5. 7.2.2.2.5 SEPIC Capacitor Selection
          6. 7.2.2.2.6 Input Capacitor Selection
          7. 7.2.2.2.7 Output Capacitor Selection
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Custom Design with WEBENCH Tools
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

VIN= 12 V, RFA= 40 kΩ, TJ = 25°C, unless otherwise indicated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback Voltage VCOMP = 1.4 V, 2.97 ≤ VIN ≤ 48 V 1.275 V
VCOMP = 1.4 V, 2.97 ≤ VIN ≤ 48 V, –40°C ≤ TJ ≤ 125°C 1.256 1.294
ΔVLINE Feedback Voltage Line Regulation 2.97 ≤ VIN ≤ 48 V 0.003 %/V
ΔVLOAD Output Voltage Load Regulation IEAO Source/Sink ±0.5 %/A
VUVLOSEN Undervoltage Lockout Reference Voltage VUVLO Ramping Down 1.430 V
VUVLO Ramping Down, –40°C ≤ TJ ≤ 125°C 1.345 1.517
IUVLO UVLO Source Current Enabled 5 µA
Enabled, –40°C ≤ TJ ≤ 125°C 3 6
VUVLOSD UVLO Shutdown Voltage 0.55 0.7 0.82 V
ICOMP COMP pin Current Source VFB = 0V 640 µA
VCOMP VFB = 1.275V 1.4 V
fnom Nominal Switching Frequency RFA = 40 kΩ 475 kHz
RFA = 40 kΩ, –40°C ≤ TJ ≤ 125°C 406 550
Vsync-HI Threshold for Synchronization on FA/SYNC/SD pin Synchronization Voltage Rising 1.4 V
Vsync-LOW Threshold for Synchronization on FA/SYNC/SD pin Synchronization Voltage Falling 0.7 V
RDS1 (ON) Driver Switch On Resistance (top) IDR = 0.2A, VIN= 5 V 4 Ω
RDS2 (ON) Driver Switch On Resistance (bottom) IDR = 0.2A 2 Ω
VDR (max) Maximum Drive Voltage Swing(1) VIN < 6V VIN V
VIN ≥ 6V 6
Dmax Maximum Duty Cycle RFA=40 kΩ 81 85 %
tmin (on) Minimum On Time 250 363 ns
worst case over temperature 571 ns
ISUPPLY Supply Current (switching) See(2) 3.7 mA
See(2), –40°C ≤ TJ ≤ 125°C 5.0
IQ Quiescent Current in Shutdown Mode VFA/SYNC/SD = 3 V(3), VIN = 12 V 9 µA
VFA/SYNC/SD = 3 V(3), VIN = 12 V, –40°C ≤ TJ ≤ 125°C 15
VFA/SYNC/SD = 3 V(3), VIN = 5 V 5
VFA/SYNC/SD = 3 V(3), VIN = 5 V, –40°C ≤ TJ ≤ 125°C 10
VSENSE Current Sense Threshold Voltage 160 mV
–40°C ≤ TJ ≤ 125°C 100 190
VSC Short Circuit Current Limit Sense Voltage 220 mV
–40°C ≤ TJ ≤ 125°C 157 275
VSL Internal Compensation Ramp Voltage 90 mV
VOVP Output Over-voltage Protection (with respect to feedback voltage)(4) VCOMP = 1.4 V 85 mV
VCOMP = 1.4 V, –40°C ≤ TJ ≤ 125°C 26 135
VOVP(HYS) Output Over-Voltage Protection Hysteresis VCOMP = 1.4 V 70 mV
VCOMP = 1.4 V, –40°C ≤ TJ ≤ 125°C 28 106
Gm Error Amplifier Transconductance VCOMP = 1.4 V 450 µS
VCOMP = 1.4 V, –40°C ≤ TJ ≤ 125°C 216 690
AVOL Error Amplifier Voltage Gain VCOMP = 1.4 V, IEAO = 100 µA (Source/Sink) 60 V/V
VCOMP = 1.4 V, IEAO = 100 µA (Source/Sink), –40°C ≤ TJ ≤ 125°C 35 66
IEAO Error Amplifier Output Current (Source/ Sink) Source, VCOMP = 1.4 V, VFB = 0 V 640 µA
Source, VCOMP = 1.4 V, VFB = 0 V, –40°C ≤ TJ ≤ 125°C 475 837
Sink, VCOMP = 1.4 V, VFB = 1.4 V 65 µA
Sink, VCOMP = 1.4 V, VFB = 1.4 V, –40°C ≤ TJ ≤ 125°C 31 100
VEAO Error Amplifier Output Voltage Swing Upper Limit: VFB = 0 V, COMP Pin Floating 2.70 V
Upper Limit: VFB = 0 V, COMP Pin Floating, –40°C ≤ TJ ≤ 125°C 1.8 2.93
Lower Limit: VFB = 1.4 V 0.60 V
Lower Limit: VFB = 1.4 V, –40°C ≤ TJ ≤ 125°C 0.32 0.90
tSS Internal Soft-Start Delay VFB = 1.2 V, COMP Pin Floating 8.7 15 21.3 ms
tr Drive Pin Rise Time Cgs = 3000 pf, VDR = 0 V to 3 V 25 ns
tf Drive Pin Fall Time Cgs = 3000 pf, VDR = 3 V to 0 V 25 ns
VSD Shutdown signal threshold(5)FA/SYNC/SD pin Output = High (Shutdown) 1.31 V
Output = High (Shutdown), –40°C ≤ TJ ≤ 125°C 1.40
Output = Low (Enable) 0.68 V
Output = Low (Enable), –40°C ≤ TJ ≤ 125°C 0.40
ISD Shutdown Pin Current FA/SYNC/SD pin VSD = 5 V −1 µA
VSD = 0 V 20
TSD Thermal Shutdown 165 °C
Tsh Thermal Shutdown Hysteresis 10 °C
(1) The drive pin voltage, VDR, is equal to the input voltage when input voltage is less than 6 V. VDR is equal to 6 V when the input voltage is greater than or equal to 6 V.
(2) For this test, the FA/SYNC/SD Pin is pulled to ground using a 40-kΩ resistor.
(3) For this test, the FA/SYNC/SD Pin is pulled to 3 V using a 40-kΩ resistor.
(4) The overvoltage protection is specified with respect to the feedback voltage. This is because the overvoltage protection tracks the feedback voltage. The overvoltage threshold can be calculated by adding the feedback voltage (VFB) to the overvoltage protection specification.
(5) The FA/SYNC/SD pin should be pulled high through a resistor to turn the regulator off. The voltage on the FA/SYNC/SD pin must be above the max limit for the Output = High longer than 30 µs to keep the regulator off and must be below the minimum limit for Output = Low to keep the regulator on.