SNVU679 September 2019 LP8733
Table 8 lists the register bit values loaded from the OTP memory during device start-up.
Address | Register Name | Bit | LP873347 Value |
---|---|---|---|
0x00 | DEV_REV | DEVICE_ID[1:0] | 0h |
0x01 | OTP_REV | OTP_ID[7:0] | 47h |
0x02 | BUCK0_CTRL_1 | BUCK0_FPWM | 0h |
0x02 | BUCK0_CTRL_1 | BUCK0_EN_PIN_CTRL | 1h |
0x02 | BUCK0_CTRL_1 | BUCK0_EN | 1h |
0x03 | BUCK0_CTRL_2 | BUCK0_ILIM[2:0] | 5h |
0x03 | BUCK0_CTRL_2 | BUCK0_SLEW_RATE[2:0] | 4h |
0x04 | BUCK1_CTRL_1 | BUCK1_FPWM | 0h |
0x04 | BUCK1_CTRL_1 | BUCK1_EN_PIN_CTRL | 1h |
0x04 | BUCK1_CTRL_1 | BUCK1_EN | 1h |
0x05 | BUCK1_CTRL_2 | BUCK1_ILIM[2:0] | 5h |
0x05 | BUCK1_CTRL_2 | BUCK1_SLEW_RATE[2:0] | 4h |
0x06 | BUCK0_VOUT | BUCK0_VSET[7:0] | 39h |
0x07 | BUCK1_VOUT | BUCK1_VSET[7:0] | 43h |
0x08 | LDO0_CTRL | LDO0_EN_PIN_CTRL | 1h |
0x08 | LDO0_CTRL | LDO0_EN | 1h |
0x09 | LDO1_CTRL | LDO1_EN_PIN_CTRL | 1h |
0x09 | LDO1_CTRL | LDO1_EN | 1h |
0x0A | LDO0_VOUT | LDO0_VSET[4:0] | 4h |
0x0B | LDO1_VOUT | LDO1_VSET[4:0] | 1h |
0x0C | BUCK0_DELAY | BUCK0_SHUTDOWN_DELAY[3:0] | Ch |
0x0C | BUCK0_DELAY | BUCK0_STARTUP_DELAY[3:0] | 0h |
0x0D | BUCK1_DELAY | BUCK1_SHUTDOWN_DELAY[3:0] | Ah |
0x0D | BUCK1_DELAY | BUCK1_STARTUP_DELAY[3:0] | 2h |
0x0E | LDO0_DELAY | LDO0_SHUTDOWN_DELAY[3:0] | 0h |
0x0E | LDO0_DELAY | LDO0_STARTUP_DELAY[3:0] | Ch |
0x0F | LDO1_DELAY | LDO1_SHUTDOWN_DELAY[3:0] | Ch |
0x0F | LDO1_DELAY | LDO1_STARTUP_DELAY[3:0] | 0h |
0x10 | GPO_DELAY | GPO_SHUTDOWN_DELAY[3:0] | Ch |
0x10 | GPO_DELAY | GPO_STARTUP_DELAY[3:0] | 1h |
0x11 | GPO2_DELAY | GPO2_SHUTDOWN_DELAY[3:0] | 0h |
0x11 | GPO2_DELAY | GPO2_STARTUP_DELAY[3:0] | 0h |
0x12 | GPO_CTRL | GPO2_OD | 1h |
0x12 | GPO_CTRL | GPO2_EN_PIN_CTRL | 0h |
0x12 | GPO_CTRL | GPO2_EN | 0h |
0x12 | GPO_CTRL | GPO_OD | 1h |
0x12 | GPO_CTRL | GPO_EN_PIN_CTRL | 1h |
0x12 | GPO_CTRL | GPO_EN | 1h |
0x13 | CONFIG | STARTUP_DELAY_SEL | 1h |
0x13 | CONFIG | SHUTDOWN_DELAY_SEL | 1h |
0x13 | CONFIG | CLKIN_PIN_SEL | 0h |
0x13 | CONFIG | CLKIN_PD | 1h |
0x13 | CONFIG | EN_PD | 1h |
0x13 | CONFIG | TDIE_WARN_LEVEL | 0h |
0x13 | CONFIG | EN_SPREAD_SPEC | 0h |
0x14 | PLL_CTRL | EN_PLL | 0h |
0x14 | PLL_CTRL | EXT_CLK_FREQ[4:0] | 1h |
0x15 | PGOOD_CTRL_1 | PGOOD_POL | 0h |
0x15 | PGOOD_CTRL_1 | PGOOD_OD | 1h |
0x15 | PGOOD_CTRL_1 | PGOOD_WINDOW_LDO | 1h |
0x15 | PGOOD_CTRL_1 | PGOOD_WINDOW_BUCK | 1h |
0x15 | PGOOD_CTRL_1 | EN_PGOOD_LDO1 | 1h |
0x15 | PGOOD_CTRL_1 | EN_PGOOD_LDO0 | 1h |
0x15 | PGOOD_CTRL_1 | EN_PGOOD_BUCK1 | 1h |
0x15 | PGOOD_CTRL_1 | EN_PGOOD_BUCK0 | 1h |
0x16 | PGOOD_CTRL_2 | EN_PGOOD_TWARN | 0h |
0x16 | PGOOD_CTRL_2 | PG_FAULT_GATES_PGOOD | 0h |
0x16 | PGOOD_CTRL_2 | PGOOD_MODE | 0h |
0x20 | TOP_MASK_1 | PGOOD_INT_MASK | 1h |
0x20 | TOP_MASK_1 | SYNC_CLK_MASK | 1h |
0x20 | TOP_MASK_1 | TDIE_WARN_MASK | 1h |
0x20 | TOP_MASK_1 | I_MEAS_MASK | 1h |
0x21 | TOP_MASK_2 | RESET_REG_MASK | 1h |
0x22 | BUCK_MASK | BUCK1_PGF_MASK | 1h |
0x22 | BUCK_MASK | BUCK1_PGR_MASK | 1h |
0x22 | BUCK_MASK | BUCK1_ILIM_MASK | 1h |
0x22 | BUCK_MASK | BUCK0_PGF_MASK | 1h |
0x22 | BUCK_MASK | BUCK0_PGR_MASK | 1h |
0x22 | BUCK_MASK | BUCK0_ILIM_MASK | 1h |
0x23 | LDO_MASK | LDO1_PGF_MASK | 1h |
0x23 | LDO_MASK | LDO1_PGR_MASK | 1h |
0x23 | LDO_MASK | LDO1_ILIM_MASK | 1h |
0x23 | LDO_MASK | LDO0_PGF_MASK | 1h |
0x23 | LDO_MASK | LDO0_PGR_MASK | 1h |
0x23 | LDO_MASK | LDO0_ILIM_MASK | 1h |