SNVU753A November   2019  – May 2021 TPS542A52

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A52EVM-059 PCB
  4. 3TPS542A52EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A52EVM-059 Top Circuit (Small Layout Area Design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A52EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A52EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

4.3.1 Input/Output Connections

The TPS542A52EVM-059 is provided with input/output connectors and test points as shown in Table 4-2. A power supply capable of supplying at least 5 A at the desired EVM input voltage must be connected to J1_2 through a pair of 20-AWG or greater wires. The load must be connected to J2_2 through a pair of 18-AWG or greater wires. The maximum load current capability of the top ciricuit is 12 A, as limited by R7_2.

Wire lengths must be minimized to reduce losses and parasitic inductance in the wires. PVIN+_2 (TP1_2) provides a tets point to monitor the VIN input voltages with PVIN-_2 (TP2_2) providing a convenient reference to PGND. VOUT+_2 (TP6_2) is used to monitor the output voltage with VOUT-_2 (TP7_2) providing a reference to PGND.

Table 4-2 Bottom Circuit Connections and Test Points
CONNECTION AND TEST POINTSDESCRIPTION
J1_2VIN, PGND connection (see Table 1-1 for input voltage range)
J2_2VOUT, PGND connection: 5.5 V at 15 A maximum (default is 1 V out at 12 A)
J3_2Enable configuration
J4_2Output current sensing points when using function generator as load control signal
PVIN+_2 (TP1_2), PVIN-_2 (TP2_2)VIN voltage sensing test points
VOUT+_2 (TP6_2), VOUT-_2 (TP7_2)VOUT voltage sensing test points
AVIN_2 (TP3_2)AVIN voltage sensing test points
VREG_2 (TP4_2)VREG voltage sensing test point
SW+_2 (TP5_2), SW-_2 (TP18_2)SW node sensing test points
CHA_2 (TP9_2), CHB_2 (TP8_2)Loop measurement test points
SCL2 (TP10_2), SDA2 (TP11_2)Not used in this EVM
EN_2 (TP14_2)EN pin test point
PGD_2 (TP13_2)Open-drain PGD test point
SYNC2 (TP12_2)For connecting and measuring external clock synchronization
AGND_2 (TP15_2, TP16_2, TP17_2)AGND connection - multiple provided to reduce oscilloscope ground probe loop inductance
PGND_2 (TP18_2, TP19_2)PGND connection
FGEN+_2 (TP20_2), FGEN-_2 (TP21_2)Function generator connection points - referenced to PGND