SNVU760 February   2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
    2. 1.2 TPS3704x-Q1 Applications
  3. 2Schematic, Bill of Materials, and Layout
    1. 2.1 TPS3704Q1EVM Schematic
    2. 2.2 TPS3704Q1EVM Bill of Materials
    3. 2.3 Layout and Component Placement
    4. 2.4 Layout
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Supply Voltage (VDD)
    2. 4.2 Monitoring Input Voltage
    3. 4.3 Default Reset Outputs (RESET1 and RESET2)
    4. 4.4 Optional Reset Output (RESET3)
  6. 5Revision History

4.1 Supply Voltage (VDD)

Test point TP11 is used to supply VDD to the TPS3704x-Q1, this test point also supplies the pull-up voltage for RESET1, RESET2, and RESET3 through jumpers J9, J10, and J11 respectively. The recommended VDD supply voltage range for the TPS3704x-Q1 is 1.7 V to 6 V. The absolute maximum ratings can be found in the device datasheet.

In the default EVM configuration, RESET1 and RESET2 will follow VDD as shown in Figure 4-1. The voltage blips seen on RESET2 when VDD approaches zero are related to the power on reset voltage, VPOR, which is the minimum VDD voltage level for a controlled output state. The device datasheet should be consulted for more information on VPOR for this device. Figure 4-2 shows the reset delay time of RESET1 and RESET2 due to VDD while input voltages VIN1 through VIN4 are all held within their respective voltage window thresholds.

GUID-20210209-CA0I-N3PZ-HP4X-KBM3TBGKLKBF-low.svgFigure 4-1 VDD Ramp
GUID-20210125-CA0I-VRQZ-PDZ6-T9T0FMM1B0PT-low.svgFigure 4-2 Reset Delay (tD) due to VDD