SNVU768 December   2021 LM63460-Q1 , LM64460-Q1

 

  1.   Trademarks
  2. 1High-Density EVM Description
    1. 1.1 Typical Applications
    2. 1.2 Features and Electrical Performance
  3. 2EVM Performance Specifications
  4. 3EVM Photo
  5. 4Test Setup and Procedure
    1. 4.1 EVM Connections
    2. 4.2 EVM Setup
    3. 4.3 Test Equipment
    4. 4.4 Recommended Test Setup
      1. 4.4.1 Input Connections
      2. 4.4.2 Output Connections
    5. 4.5 Test Procedure
      1. 4.5.1 Line/Load Regulation and Efficiency
  6. 5Test Data and Performance Curves
    1. 5.1 Conversion Efficiency
    2. 5.2 Output Voltage Regulation
    3. 5.3 Operating Waveforms
      1. 5.3.1 Start-Up and Enable ON/OFF
      2. 5.3.2 Line and Load Transients
      3. 5.3.3 Short Circuit and Recovery
    4. 5.4 Thermal Performance
    5. 5.5 EMI Results – CISPR 25 Class 5
      1. 5.5.1 Conducted EMI
      2. 5.5.2 Radiated EMI
  7. 6EVM Documentation
    1. 6.1 Schematics
      1. 6.1.1 LM63460EVM-2MHZ Schematic
      2. 6.1.2 LM64460EVM-2MHZ Schematic
    2. 6.2 Bill of Materials
      1. 6.2.1 Alternative BOM Configurations
    3. 6.3 PCB Layout
    4. 6.4 Assembly Drawings
  8. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Custom Design With WEBENCH® Tools
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation

6.1.1 LM63460EVM-2MHZ Schematic

Figure 6-1 shows the schematic for the LM63460EVM-2MHZ. Suitable component placements configure the EVM to accommodate the EN/SYNC and RT pin features of the LM63460-Q1. More specifically, C20 (1 nF) connects SYNC from header J3 to the EN/SYNC pin of the LM63460-Q1, and R11 (6.04 kΩ) sets the switching freqeunecy at 2.1 MHz.

Figure 6-1 LM63460-Q1 EVM Schematic