SNVU772 November   2021 LP8733

 

  1.   Trademarks
  2. 1Introduction
  3. 2OTP Memory Device Settings
  4. 3Power-up and Power Down Sequence
  5. 4Register Bits Loaded From OTP Memory

3 Power-up and Power Down Sequence

This section shows the power-up and power-down sequence for the device. The power-up and power-down delays for each rail are shown in Figure 3-1.

Figure 3-1 LP873345 Power-up and Power Down Sequence