SNVU804 May   2022 LP8732-Q1

 

  1.   Trademarks
  2. 1Technical Reference Manual
  3. 1Introduction
  4. 2OTP Memory Device Settings
  5. 3Power-up and Power Down Sequence
  6. 4Register Bits Loaded From OTP Memory

3 Power-up and Power Down Sequence

This section shows the power-up and power-down sequence for the device. The power-up and power-down delays for each rail are shown in Figure 3-1.

Figure 3-1 LP873248-Q1 Power-up and Power Down Sequence