SNVU816 October   2021 LP87565-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Sequencing
  4. 3Register Bits Loaded From OTP Memory

1 Introduction

This technical reference manual can be used as a reference for the LP87565U-Q1 default register bits after power up. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the datasheet.

Table 1-1 provides the quick overview of each regulator default OTP settings. Section 2 provides an overview of default power up and power down sequence. Table 3-1 lists all the default OTP settings after power up.

Table 1-1 Main OTP Settings for regulators
DescriptionBit Name Value
Device identification OTP configuration OTP_ID D0h
BUCK0+BUCK1 (2-phase operation)Output voltageBUCK0_VSET900 mV
Enable (ENx pin or I2C register write)EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT EN1 pin
Startup delayBUCK0_STARTUP_DELAY8 ms
Shutdown delayBUCK0_SHUTDOWN_DELAY12 ms
Force PWM BUCK0_FPWM Forced PWM
Force multiphase BUCK0_FPWM _MP Forced multi-phase operation
Peak current limitILIM0, ILIM15.0 A
Maximum load currentN/A8 A
Slew rateSLEW_RATE03.8 mV/us
BUCK2+BUCK3 (2-phase operation) Output voltage BUCK2_VSET 820 mV
Enable (ENx pin or I2C register write) EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECT EN1 pin
Startup delay BUCK2_STARTUP_DELAY 6 ms
Shutdown delay BUCK2_SHUTDOWN_DELAY 14 ms
Force PWM BUCK2_FPWM Forced PWM
Force multiphase BUCK2_FPWM _MP Forced multi-phase operation
Peak current limit ILIM2 5.0 A
Maximum load current N/A 8 A
Slew rate SLEW_RATE2 3.8 mV/us
Spread spectrum EN_SPREAD_SPEC Enabled
Switching frequency N/A 2 MHz
I2C addressN/A60h