SNVU817 November   2021 LMR38020-Q1

 

  1.   Trademarks
  2. 1General TI High Voltage Evaluation User Safety Guidelines
  3. 2 LMR38020-Q1 Evaluation Module
    1. 2.1 Quick Start Procedure
    2. 2.2 Detailed Descriptions
  4. 3Schematic
  5. 4PCB Layout
  6. 5Bill of Materials

PCB Layout

Figure 4-1 through Figure 4-4 show the board layout for the LMR38020QEVM. The EVM offers resistors, capacitors, and test points to configure the output voltage, precision enable, and switching frequency.

The 8-pin SO PowerPAD™ package offers an exposed thermal pad, which must be soldered to the copper landing on the PCB for optimal thermal performance. The PCB consists of a 4-layer design. There are 2-oz copper planes on the top and bottom and 1-oz copper mid-layer planes to dissipate heat with an array of thermal vias under the thermal pad to connect to all four layers.

Test points have been provided for ease of use to connect the power supply, required load, and to monitor critical signals.

GUID-20211102-SS0I-PP52-XH9F-RBK2PPSPVFHH-low.pngFigure 4-1 Top Layer and Silkscreen Layer
GUID-20211102-SS0I-XBLR-QRCT-0PVHRKMXL3HF-low.pngFigure 4-2 Mid-Layer 1 Ground Plane
GUID-20211102-SS0I-DLXV-LBFV-32DX8LFPWTSV-low.pngFigure 4-3 Mid-Layer 2 Routing
GUID-20211102-SS0I-NJTN-TPRB-HRJDSTMPKR4D-low.pngFigure 4-4 Bottom Layer Routing