SNVU820 February   2022 LM5149-Q1

 

  1.   Trademarks
  2. 1High Density EVM Description
    1. 1.1 Typical Applications
    2. 1.2 Features and Electrical Performance
  3. 2EVM Characteristics
  4. 3Application Circuit Diagram
  5. 4EVM Photo
  6. 5Test Setup and Procedure
    1. 5.1 EVM Connections
    2. 5.2 Test Equipment
    3. 5.3 Recommended Test Setup
      1. 5.3.1 Input Connections
      2. 5.3.2 Output Connections
    4. 5.4 Test Procedure
      1. 5.4.1 Line and Load Regulation, Efficiency
  7. 6Test Data and Performance Curves
    1. 6.1 Conversion Efficiency
    2. 6.2 Operating Waveforms
      1. 6.2.1 Switching
      2. 6.2.2 Load Transient Response
      3. 6.2.3 Line Transient Response
      4. 6.2.4 Start-Up and Shutdown With EN
      5. 6.2.5 Start-Up and Shutdown with VIN
    3. 6.3 Bode Plot
    4. 6.4 CISPR 25 EMI Performance
    5. 6.5 Thermal Performance
  8. 7EVM Documentation
    1. 7.1 Schematic
    2. 7.2 List of Materials
    3. 7.3 PCB Layout
    4. 7.4 Component Drawings
  9. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources

7.3 PCB Layout

Figure 7-2 through Figure 7-9 show the design of the LM5149-Q1 EVM using a six-layer PCB with 2-oz copper thickness. The power stage is essentially a single-sided design and the input filtering is located on the bottom side.

Figure 7-2 Top Copper (Top View)
Figure 7-3 Layer 2 Copper (Top View)
Figure 7-4 Layer 3 Copper (Top View)
Figure 7-5 Layer 4 Copper (Top View)
Figure 7-6 Layer 5 Copper (Top View)
Figure 7-7 Bottom Copper (Top View)