SNVU843A April   2023  – November 2023

 

  1.   1
  2.   LM5171 Evaluation Module
  3.   Trademarks
  4. 1Features and Electrical Performance
  5. 2Setup
    1. 2.1 EVM Configurations
    2. 2.2 Bench Setup
    3. 2.3 Test Equipment
    4. 2.4 Jumper Settings for Typical Operation Modes
      1. 2.4.1 Buck Mode with Voltage Regulation
      2. 2.4.2 Boost Mode with Voltage Regulation
      3. 2.4.3 Buck Mode with Current Regulation
      4. 2.4.4 Boost Mode with Current Regulation
      5. 2.4.5 2-EVM Daisy-Chain for 3 or 4-Phase Operation
  6. 3Test Procedure
    1. 3.1 Buck Mode Power-Up and Power-Down Sequence
    2. 3.2 Boost Mode Power-Up and Power-Down Sequence
    3. 3.3 Bidirectional Operation Power-Up and Power-Down Sequence
    4. 3.4 Operating the EVM With External MCU or Other Digital Circuit
  7. 4Test Data
    1. 4.1 Efficiency
    2. 4.2 Step Load Response
    3. 4.3 Dual-Channel Interleaving Operation
    4. 4.4 Typical Start Up and Shutdown
    5. 4.5 DEM and FPWM
    6. 4.6 Mode transition between DEM and FPWM
    7. 4.7 ISET Tracking
    8. 4.8 Pre-charge
    9. 4.9 Protections
  8. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 Board Layout
  9. 6Revision History

2.1 EVM Configurations

Figure 2-8 shows the EVM board top view and circuit layout partitions. The EVM has the following ports:

  • 48VDC-Port: Connected to 48-V battery rail
  • 12VDC-Port: Connected to 12-V battery rail
  • J17 (60-Pin Header): Interfacing the external control commands or MCU
  • J18 (60-Pin Header): Interfacing J17 of the secondary EVM in a 4-phase system consisting of two EVMs
  • Channel Current Setting: Analog programming at J17-pin 11, and digital programming at J17-pin 13
  • I2C interface for diagnosis and monitory functions at J45.

Table 2-1 through Table 2-4 list the functions of the EVM jumpers and headers. The EVM jumpers and headers offer flexible configurability and programmability of the EVM for various use cases including but not limited to the following:

  • A unidirectional or bidirectional voltage source
  • A unidirectional or bidirectional current source
  • Dynamic phase adding and shedding in a 4-phase system consisting of two EVMs
  • Dynamic MOSFETs dead time adjustment
  • Individual channel current monitoring or total current monitoring
  • Synchronization to external clock
  • External shutdown command through DT/nSD pin (J17-pin45)

GUID-20231107-SS0I-PDR4-JXTR-VQCV28DWXZG6-low.svg Figure 2-1 Simplified EVM Schematic
GUID-20230324-SS0I-CQFF-X2CB-CT2QMD9NLCLL-low.svg Figure 2-2 EVM Board Top View and Layout Partitions
Table 2-1 Three-Pin Header Settings
HEADERSIGNALPINSFUNCTION DESCRIPTIONDEFAULT
J1UVLO--(1)

External UVLO command through J17

(1,2)(2)48VDC-Port UVLO ControlY
(2,3)(3)12VDC-Port UVLO Control
J6OPT--External interleaving control through J17
(1,2)CH-2 240 degree delay from CH-1
(2,3)CH-2 180 degree delay from CH-1Y
J13 SYNC -- Secondary EVM not sync to main EVM Y
(1,2) Secondary EVM sync to main EVM
(2,3) Secondary EVM sync to external clock
J26OTEMP--Onboard Over temperature protection inactiveY
(1,2)Over temperature protection in hiccup mode
(2,3)Over temperature protection in latched shutdown
J28DIR--External DIR control through J17
(1,2)Onboard DIR command for buck operationY
(2,3)Onboard DIR command for boost operation
J29EN1--External CH-1 enable control through J17
(1,2)Onboard CH-1 enableY
(2,3)Onboard CH-1 inactive
J30EN2--External CH-2 enable control through J17, overridden by J24.Y
(1,2)Onboard CH-2 enable
(2,3)Onboard CH-2 inactive
J34CFG--I2C address set to 0x0 is not selected
(1,2)

I2C address set to 0x0, and select inductor current monitor

Y
(2,3)

I2C address set to 0x0, and select output current monitor

J35 CFG -- I2C address set to 0x1 is not selected Y
(1,2)

I2C address set to 0x1, and select inductor current monitor
(2,3)

I2C address set to 0x1, and select output current monitor
J36 ISET -- External ISET control through J17
(1,2)

Onboard voltage loop

 Y
(2,3)

External digital voltage loop
(1) – = All jumper pins open.
(2) (1,2) = Pins 1 and 2 closed.
(3) (2,3) = Pins 2 and 3 closed.
Table 2-2 Two-Pin Header Settings
HEADERSIGNALPINSFUNCTION DESCRIPTIONDEFAULT
J2IMON1C(1) IMON1 filter connectedY
O(2)IMON1 filter disconnected
J3nSDCShutdown
O External shutdown via J17Y
J4SS/DEM1CCH-1 set to DEMY
OCH-1 set to FPWM
J5SS/DEM2CCH-2 set to DEMY
OCH-2 set to FPWM
J7IMON2CIMON2 filter connectedY
OIMON2 filter disconnected
J12DitheringCdithering control allowed
Odithering control not allowedY
J14SQINCNot allowed
Osquare wave input for dithering controlY
J15SS/DEM1 & SS/DEM2CSS/DEM1 & SS/DEM2 are connectedY
OSS/DEM1 & SS/DEM2 are independent
J16 Main & Secondary EVM IMON1 C Main EVM & Secondary EVM IMON1 signal merged
O Main EVM & Secondary EVM IMON1 signal not merged Y
J19Main & Secondary EVM 10 V VCCCMain EVM & Secondary EVM 10 V VCC connected
OMain EVM & Secondary EVM 10 V VCC not connectedY
J20Main & Secondary EVM SD_CMDCMain EVM & Secondary EVM SD_CMD connected for simultaneous shutdown
OMain EVM & Secondary EVM SD_CMD not connected for independent shutdownY
J21IMON1 & IMON2C Combined channel current monitors
OIndependent dual-channel current monitorY
J22Main & Secondary EVM UVLOCMain EVM & Secondary EVM UVLO connected
OMain EVM & Secondary EVM UVLO not connectedY
J23Main & Secondary EVM EN1CMain EVM & Secondary EVM EN1 connected
OMain EVM & Secondary EVM EN1 not connectedY
J24EN1 & EN2CCombined channel enableY
OIndependent dual-channel enable
J25USB2ANY pullup for SCLC Pullup by USB2ANY board
O

Pullup by external signal source through J17

Y
J32OPT/ EN2_secondaryC3- and 4-phase auto transition
O3- and 4-phases auto transition inactiveY
J33PWM input for ISETCNot allowed
OExternal PWM input for ISET Y
J37

VSET input

CNot allowed
OOutput voltage tracking inputY
J38

Onboard bias supply output connection

C

VCC supplied by onboard VCC.

Y
O

Onboard bias supply output disconnected from VCC.

J39External VCC supply inputCNot allowed
OExternal 10-12V input port for VCCY
J40

Onboard bias supply

enable

COnboard bias supply enabledY
OOnboard bias supply inactive
J41 Onboard bias supply input connection C

Sepic input is energized by 48V-port

 Y
O

Sepic input is disconnected and not energized
J42 CC Control C

CC control allowed
O CC control inactive Y
J43 CC Control Input C Not allowed
O CC control input port Y
J44 USB2ANY pullup for SDA C Pullup by USB2ANY board
O Pullup by external signal source through J17 Y
(1) Jumper pins closed.
(2) Jumper pins open.
Table 2-3 J17 60-Pin Header Description(1)
PIN SIGNAL I/O DESCRIPTION
1 V48SN O(2) 48V-port voltage sense during operation
3 V12SN O 12V-port voltage sense during operation
5 UVLO I(3) Main EVM enable (connect to the UVLO pin of the IC)
7 EN1 I CH-1 control (connect to the EN1 pin of the IC)
9 DIR I Direction command
11 ISETA I Analog command for ISET
13 ISETD I Digital PWM command for ISET
15 SYNCIN I Input of the external clock to be synchronized to
17 SYNCOUT O Clock output signal
19 OPT I Interleave angle setting
21 EN2 I CH-2 control (connect to the EN2 pin of the IC)
23 DEM O FPWM/DEM selection
25 +5V O Onboard 5 V bias supply
27 IMON1 O CH-1 monitor
29 IMON2 O CH-2 current monitor
31 IMON1_S O Secondary EVM CH-1 monitor in 3 or 4 phases
33 IMON2_S O Secondary EVM CH-2 current monitor in 3 or 4 phases
35 AGND I/O Reference GND for control signals
37 PGND O Power ground of the DC-DC converter
39 SDA I SDA of I2C
41 SCL I SCL of I2C
43 +10 V I/O +10V bias supply
45 nSD I/O External shut down command input pin
47 ENABLE_S I Secondary EVM enable (connect to the UVLO pin of the secondary IC)
49 CH1_S I Secondary EVM CH-1 control (connect to the EN1 pin of the secondary IC)
51 CH2_S I Secondary EVM CH-2 control (connect to the EN2 pin of the secondary IC)
53 SYNCIN_S I Input of the external clock for the secondary EVM to be synchronized to
55 SYNCOUT_S O Secondary EVM clock output signal
57 nSD_S I/O Secondary EVM external shut down command input pin
59 KEY — No Connect
All even number pins AGND I/O All signals’ return
(1) J17 is the interface connector to MCU, or external digital controller, or to J18 of the main EVM if the host EVM serves as a secondary EVM in the multiphase configuration.
(2) I = input pin
(3) O = output pin
Table 2-4 J18 60-Pin Header Description(1)
PINSIGNALI/ODESCRIPTION
1V48_X—No Connect
3V12_X—No Connect
5ENABLE_SI(2)Secondary EVM enable (connect to the UVLO pin of the secondary IC)
7CH1_SISecondary EVM CH-1 control (connect to the EN1 pin of the IC)
9DIRIDirection command
11ISETAIAnalog command for ISET
13ISETDIDigital PWM command for ISET
15SYNCIN_SIThe external clock input for the secondary
17SYNCOUT_SO(3)Secondary EVM clock output signal
19OPTIInterleave angle setting
21CH2_SISecondary EVM CH-2 control (connect to the EN1 pin of the IC)
23DEM_SIFPWM/DEM selection
25+5 VIOnboard 5 V bias supply
27IMON1_SOSecondary EVM CH-1 monitor in 3 or 4 phases
29IMON2_SOSecondary EVM CH-2 current monitor in 3 or 4 phases
31IMON1_X—Not used
33IMON2_X—Not used
35AGNDI/OReference GND for control signals
37PGNDOPower ground of the DC-DC converter
39SDAISDA of I2C
41SCL—SCL of I2C
43+10 VIOnboard +10-V bias supply
45nSD_SI/OSecondary EVM external shut down command input pin
47UVLO_X—No Connect
49CH1_X—No Connect
51CH2_X—No Connect
53SYNCIN_X—No Connect
55SYNCOUT_X—No Connect
57SD_X—No Connect
59KEY—No Connect
All even number pinsAGNDI/OAll signals’ return
(1) J18 is the interface connector to the secondary EVM in the multiphase configuration if the host EVM serves as the main. All control commands and control signals are sent through J18 to J17 of the secondary EVM.
(2) I = input pin
(3) O = output pin