SNVU852B September   2023  – June 2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Connector, Test Point, and Selection Switch Descriptions
      1. 2.1.1 Connector Descriptions
      2. 2.1.2 Jumper Descriptions
      3. 2.1.3 Test Point Descriptions
      4. 2.1.4 Selection Switch Descriptions
        1. 2.1.4.1 S1 and S2 CFG Setting
      5. 2.1.5 I2C Operation
  9. 3Implementation Results
    1. 3.1 Test Setup and Procedure
      1. 3.1.1 Test Setup
      2. 3.1.2 Test Procedure
      3. 3.1.3 Precautions
    2. 3.2 Test Data and Performance Curves
      1. 3.2.1 Thermal Performance
      2. 3.2.2 Efficiency
      3. 3.2.3 Steady State Waveforms
      4. 3.2.4 Step Load Response
      5. 3.2.5 AC Loop Response Curve
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Revision History

S1 and S2 CFG Setting

These switches enable to set the resistor for the CFG2 pin. Details can be found in the LM51772 data sheet.

Table 2-4 CFG2 Pin Configuration Overview
#EN_SYNC_OUTSYNC_IN_FALLINGVDET_EN

PCM_HYST_30

1DISABLEDDISABLEDDISABLED

DISABLED

2ENABLED
3DISABLEDENABLED
4ENABLED
5DISABLEDDISABLEDENABLED
6ENABLED
7DISABLEDENABLED
8ENABLED
9DISABLEDDISABLEDDISABLED

ENABLED

10ENABLED
11DISABLEDENABLED
12ENABLED
13DISABLEDDISABLEDENABLED
14ENABLED
15DISABLEDENABLED
16ENABLED
Note: Only one switch must be closed!

The remaining configuration inputs have been set to below setting:

  • CFG1:
    • Slope Factor: 1.5

  • CFG3:
    • VCC1: enabled
    • INDUCT De-rate: disabled (30%)
    • μSLEEP: enabled
    • SCALE_DT: disabled
  • CFG4:
    • DRSS: disabled
    • SCP – hiccup mode: disabled
    • Negative current limit: disabled
    • Current limit: enabled
Note: The LM51772EVM-HP has been configured with disabled I2C operation with JP8 not set. The slope compensation default setting is 1.5. This can be adjusted through I2C command or by replacing R20 with the corresponding resistor.
Note:

EVMs populated with PLM51772 do have Slope Compensation set to 0.875 and Inductor de-rate set to enabled via R2D.