SNVU862 june   2023 LP8733

 

  1.   1
  2.   Trademarks
  3.   Technical Reference Manual
  4. 1Introduction
  5. 2OTP Memory Device Settings
  6. 3Power-up and Power Down Sequence
  7. 4Register Bits Loaded From OTP Memory
  8. 5Revision History

2 OTP Memory Device Settings

This section lists all of the device settings that are downloaded from OTP memory.

Table 2-1 lists the device settings for I2C and OTP revision ID values.

Table 2-1 Device Identification and I2C Settings
Description Bit Name LP87334E
I2C address 60h
DEVICE_ID Device specific ID code DEVICE_ID 02h
OTP_ID Identification code for OTP version OTP_ID 4Eh

Table 2-2 lists the device settings for BUCK0 and BUCK1. The maximum allowed slew-rate for BUCKx depends on the output capacitance. Refer to the LP8733xx Dual High-Current Buck Converter and Dual Linear Regulator data sheet for output capacitance boundary conditions.

Table 2-2 BUCK0 and BUCK1 OTP Settings
Description Bit Name LP87334E
Buck phase configuration (2 single phase Bucks or combined 2 phase, denoted as 1+1 or 2-phase) 1+1
Switching frequency 2 MHz
Spread spectrum EN_SPREAD_SPEC Disabled
BUCK0 Output voltage BUCK0_VSET 0.850 V
Enable, EN-pin or I2C register BUCK0_EN_PIN_CTRL EN-pin
Control for BUCK0 BUCK0_EN High
Force PWM mode or auto mode BUCK0_FPWM Yes
Force Multiphase BUCK0_FPWM_MP No
Peak current limit BUCK0_ILIM 4 A
Maximum load current limit NA 3 A
Slew rate BUCK0_SLEW_RATE 7.5 mV/us
Startup delay BUCK0_STARTUP_DELAY 3 ms
Shutdown delay BUCK0_SHUTDOWN_DELAY 0.5 ms
BUCK1 Output voltage BUCK1_VSET 1.100 V
Enable, EN-pin or I2C register BUCK1_EN_PIN_CTRL EN-pin
Control for BUCK1 BUCK1_EN High
Force PWM mode or auto mode BUCK1_FPWM Yes
Peak current limit BUCK1_ILIM 4 A
Maximum load current limit NA 3 A
Slew rate BUCK1_SLEW_RATE 7.5 mV/us
Startup delay BUCK1_STARTUP_DELAY 3 ms
Shutdown delay BUCK1_SHUTDOWN_DELAY 0.5 ms

Table 2-3 lists the device settings for LDO0 and LDO1.

Table 2-3 LDO0 and LDO1 OTP Settings
Description Bit Name LP87334E
LDO0 Output voltage LDO0_VSET 0.800 V
Enable, EN-pin or I2C register LDO0_EN_PIN_CTRL EN-pin
Control for LDO0 LDO0_EN High
Startup delay LDO0_STARTUP_DELAY 1 ms
Shutdown delay LDO0_SHUTDOWN_DELAY 2.5 ms
LDO1 Output voltage LDO1_VSET 1.800 V
Enable, EN-pin or I2C register LDO1_EN_PIN_CTRL EN-pin
Control for LDO1 LDO1_EN High
Startup delay LDO1_STARTUP_DELAY 0 ms
Shutdown delay LDO1_SHUTDOWN_DELAY 3 ms

Table 2-4 lists the device settings for GPIOs.

Table 2-4 EN, CLKIN, and GPIO Pin Settings
Description Bit Name LP87334E
EN pin EN pin pulldown resistor enable or disable EN_PD Enabled
CLKIN pin CLKIN or GPO2 mode selection CLKIN_PIN_SEL GPO2
CLKIN pin pulldown resistor enable or disable (applicable for both CLKIN and GPO2 modes.) CLKIN_PD Disabled
Frequency of external clock when connected to CLKIN EXT_CLK_FREQ 2 MHz
Enable for the internal PLL. When PLL disabled, internal RC OSC is used EN_PLL Not Used
GPO GPO output type (push-pull or open drain) GPO_OD PP
Enable, EN-pin or I2C register GPO_EN_PIN_CTRL EN-pin
Control for GPO GPO_EN High
Startup delay GPO_ STARTUP_ DELAY 1 ms
Shutdown delay GPO_ SHUTDOWN_ DELAY 2.5 ms
GPO2 GPO2 output type (push-pull or open drain) GPO2_OD OD
Enable, EN-pin or I2C register GPO2_EN_PIN_CTRL EN-pin
Control for GPO2 GPO2_EN High
Startup delay GPO2_ STARTUP_ DELAY 11 ms
Shutdown delay GPO2_ SHUTDOWN_ DELAY 0 ms

Table 2-5 lists the device PGOOD settings.

Table 2-5 PGOOD OTP Settings
Description Bit Name LP87334E
Signals monitored by PGOOD BUCK0 output voltage EN_PGOOD_BUCK0 Yes
BUCK1 output voltage EN_PGOOD_BUCK1 Yes
LDO0 output voltage EN_PGOOD_LDO0 Yes
LDO1 output voltage EN_PGOOD_LDO1 Yes
Thermal warning EN_PGOOD_TWARN No
PGOOD mode selections PGOOD thresholds for BUCK0, BUCK1 (Undervoltage and Window (undervoltage and overvoltage)) PGOOD_WINDOW_BUCK Window
PGOOD thresholds for LDO0, LDO1 (Undervoltage and Window (undervoltage and overvoltage)) PGOOD_WINDOW_LDO Window
PGOOD operating mode (detecting UNUSUAL situations or detecting UNVALID situations) PGOOD_MODE Detecting UNVALID situations
PGOOD signal mode (status or latched until fault source read) PG_FAULT_GATES_PGOOD Status
PGOOD output mode (push-pull or open drain) PGOOD_OD OD
PGOOD polarity (active high or active low) PGOOD_POL Active High

Table 2-6 lists the device protection settings.

Table 2-6 Protections OTP Settings
Description Bit Name LP87334E
Protections Thermal warning level (125°C or 137°C) TDIE_WARN_LEVEL 140°C
Input overvoltage protection NA Enabled

Table 2-7 lists the device settings for interrupts. When an interrupt from an event is unmasked, an interrupt is generated on the nINT pin.

Table 2-7 Interrupt Mask Settings
Interrupt event Bit Name LP87334E
General PGOOD pin changing active to inactive PGOOD_INT_MASK Masked
Sync clock appears or disappears SYNC_CLK_MASK Masked
Thermal warning TDIE_WARN_MASK Masked
Load measurement ready I_MEAS_MASK Masked
Register reset RESET_REG_MASK Masked
BUCK0 Buck0 PGood active BUCK0_PGR_MASK Masked
Buck0 PGood inactive BUCK0_PGF_MASK Masked
Buck0 current limit BUCK0_ILIM_MASK Masked
BUCK1 Buck1 PGood active BUCK1_PGR_MASK Masked
Buck1 PGood inactive BUCK1_PGF_MASK Masked
Buck1 current limit BUCK1_ILIM_MASK Masked
LDO0 LDO0 PGood active LDO0_PGR_MASK Masked
LDO0 PGood inactive LDO0_PGF_MASK Masked
LDO0 current limit LDO0_ILIM_MASK Masked
LDO1 LDO1 PGood active LDO1_PGR_MASK Masked
LDO1 PGood inactive LDO1_PGF_MASK Masked
LDO1 current limit LDO1_ILIM_MASK Masked