SNVU864 October   2023 TPS3762-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Input Supply Voltage (VDD)
      2. 2.2.2 SENSE
      3. 2.2.3 RESET
      4. 2.2.4 Built-In Self-Test (BIST)
      5. 2.2.5 Built-In Self-Test Enable and Latch Clear (BIST_EN / LATCH_CLR)
      6. 2.2.6 RESET Time Delay (CTR)
      7. 2.2.7 Sense Time Delay (CTS)
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks

PCB Layout

Figure 5-2 and Figure 5-3 show the top and bottom assemblies of the printed circuit board (PCB) to display the component placement of the EVM.

Figure 5-4 and Figure 5-5 show the top and bottom layouts, Figure 5-6 and Figure 5-7 show the top and bottom layers, and Figure 5-8 shows the top solder mask of the EVM.

*Some board variants come with R5, C11, and C12 populated, please remove these components for proper testing of BIST functionality*

GUID-20230919-SS0I-LXG5-PWD0-TG7SWXGJZHSN-low.svgFigure 4-2 Component Placement - Top Assembly
GUID-20230919-SS0I-LTW0-FL7N-9XLM9KHNC3MK-low.svgFigure 4-4 Layout - Top
GUID-20230919-SS0I-Q6QT-3HZR-4NMGRNQ7DPGJ-low.svgFigure 4-6 Top Layer
GUID-20230919-SS0I-NNXF-Z5ZN-TQ75LGHRPD7V-low.svgFigure 4-8 Top Solder Mask
GUID-20230919-SS0I-8PTJ-V1FM-TBJV2CWTMDWM-low.svgFigure 4-3 Component Placement - Bottom Assembly
GUID-20230919-SS0I-SJTL-T1N1-P3ZGN7ZVS6TS-low.svgFigure 4-5 Layout - Bottom
GUID-20230919-SS0I-VSMW-JTXJ-DDTJ6KVJWMTM-low.svgFigure 4-7 Bottom Layer