SNVU885 January   2024 LP87523-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Sequencing
  6. 3Register Bits Loaded From OTP Memory
  7. 4Revision History

1 Introduction

This technical reference manual can be used as a reference for the LP875230E-Q1 default register bits after power up. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10A Buck Converter With Integrated Switches data sheet.

Table 1-1 provides the quick overview of each regulator default OTP settings. Section 2 provides an overview of default power up and power down sequence. Table 3-1 lists all the default OTP settings after power up.

Table 1-1 Main OTP Settings for regulators
DescriptionBit NameValue
Device identificationOTP configurationOTP_ID12h
BUCK0+BUCK1 (2-phase operation)Output voltageBUCK0_VSET1030mV
Enable (ENx pin or I2C register write)EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECTEN1 pin
Startup delayBUCK0_STARTUP_DELAY4ms
Shutdown delayBUCK0_SHUTDOWN_DELAY12ms
Force PWMBUCK0_FPWMForced PWM
Force multiphaseBUCK0_FPWM _MPForced multi-phase operation
Peak current limitILIM0, ILIM14.0A
Maximum load currentN/A6A
Slew rateN/A1.9mV/µs
BUCK2Output voltageBUCK2_VSET1800mV
Enable (ENx pin or I2C register write)EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECTEN1 pin
Startup delayBUCK2_STARTUP_DELAY0ms
Shutdown delayBUCK2_SHUTDOWN_DELAY15ms
Force PWMBUCK2_FPWMForced PWM
Peak current limitILIM23.0A
Maximum load currentN/A2A
Slew rateN/A1.9mV/µs

BUCK3

Output voltageBUCK3_VSET1350mV
Enable (ENx pin or I2C register write)EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECTEN1 pin
Startup delayBUCK3_STARTUP_DELAY8ms
Shutdown delayBUCK3_SHUTDOWN_DELAY8ms
Force PWMBUCK3_FPWMForced PWM
Peak current limitILIM33.0A
Maximum load currentN/A2A
Slew rateN/A1.9mV/µs
Spread spectrumEN_SPREAD_SPECENABLED
Switching frequencyN/A2MHz
I2C addressN/A60h