SNVU886 September   2024 TPS37100-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Input Supply Voltage (VDD)
      2. 2.2.2 SENSE
      3. 2.2.3 OUT A and OUT B
      4. 2.2.4 AEN & AOUT
      5. 2.2.5 Built-In Self-Test (BIST)
      6. 2.2.6 Built-In Self-Test Enable (BIST_EN )
      7. 2.2.7 CTR & CTS Time Delays
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks
  10. 6Revision History

2.2.6 Built-In Self-Test Enable (BIST_EN )

The BIST_EN is connected through TP11 on the board. Jumper J3 can also configure the BIST_EN pin to also connect to TP11 (Refer to Table 2-1 for configuration options).

The TPS37102-Q1 contain a Built-In Self-Test Enable (BIST_EN) pin for enabling the BIST, as well as clearing a BIST fault. The BIST_EN asserts BIST for a time period, TD_BIST. If BIST encounters a fault, then BIST remains asserted for a period longer than TD_BIST.

This pin also controls the overvoltage latch.